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  /external/dexmaker/src/dx/java/com/android/dx/dex/code/
InsnFormat.java 33 * Base class for all instruction format handlers. Instruction format
48 * dump, of the given instruction. The instruction must be of this
51 * @param insn {@code non-null;} the instruction
78 * Returns the string form of the arguments to the given instruction.
79 * The instruction must be of this instance's format. If the instruction
85 * @param insn {@code non-null;} the instruction
91 * Returns the associated comment for the given instruction, if any
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  /art/runtime/entrypoints/portable/
portable_fillarray_entrypoints.cc 30 const Instruction::ArrayDataPayload* payload =
31 reinterpret_cast<const Instruction::ArrayDataPayload*>(code_item->insns_ + payload_offset);
32 DCHECK_EQ(payload->ident, static_cast<uint16_t>(Instruction::kArrayDataSignature));
  /dalvik/dx/src/com/android/dx/io/instructions/
FillArrayDataPayloadDecodedInstruction.java 20 * A decoded Dalvik instruction which contains the payload for
21 * a {@code packed-switch} instruction.
98 throw new UnsupportedOperationException("no index in instruction");
  /dalvik/vm/mterp/armv5te/
binop.S 4 * specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
34 GOTO_OPCODE(ip) @ jump to next instruction
binop2addr.S 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
32 GOTO_OPCODE(ip) @ jump to next instruction
binopLit8.S 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
31 GOTO_OPCODE(ip) @ jump to next instruction
binopWide.S 4 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5 * This could be an ARM instruction or a function call. (If the result
37 GOTO_OPCODE(ip) @ jump to next instruction
binopWide2addr.S 4 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5 * This could be an ARM instruction or a function call. (If the result
34 GOTO_OPCODE(ip) @ jump to next instruction
  /dalvik/vm/mterp/armv6t2/
binop2addr.S 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
31 GOTO_OPCODE(ip) @ jump to next instruction
binopWide2addr.S 4 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5 * This could be an ARM instruction or a function call. (If the result
33 GOTO_OPCODE(ip) @ jump to next instruction
  /dalvik/vm/mterp/mips/
binflopWide.S 4 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5 * This could be an MIPS instruction or a function call.
50 GOTO_OPCODE(t0) # jump to next instruction
binflopWide2addr.S 4 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
5 * This could be an MIPS instruction or a function call.
44 GOTO_OPCODE(t0) # jump to next instruction
binopWide.S 4 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5 * This could be a MIPS instruction or a function call. (If the result
36 GOTO_OPCODE(t0) # jump to next instruction
binopWide2addr.S 4 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
5 * This could be a MIPS instruction or a function call. (If the result
32 GOTO_OPCODE(t0) # jump to next instruction
  /dalvik/vm/mterp/portable/
entry.cpp 18 u2 inst; // current instruction
19 /* instruction decoding */
61 FINISH(0); /* fetch and execute first instruction */
  /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/draw/
draw_pipe_aapoint.c 164 * TGSI instruction transform callback.
166 * Upon END instruction, insert texture sampling code for antialiasing.
176 /* emit our new declarations before the first instruction */
241 newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
242 newInst.Instruction.NumDstRegs = 1;
246 newInst.Instruction.NumSrcRegs = 2;
255 newInst.Instruction.Opcode = TGSI_OPCODE_ADD;
256 newInst.Instruction.NumDstRegs = 1;
260 newInst.Instruction.NumSrcRegs = 2;
272 newInst.Instruction.Opcode = TGSI_OPCODE_RSQ
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  /external/chromium_org/tools/memory_watcher/
preamble_patcher_with_stub.cc 61 // relative to the next instruction.
75 // bytes for our jmp instruction, so let's find the minimum number of
83 ASSERT(false, "Unable to patch because there is a jump instruction "
90 ASSERT(false, "Disassembler encountered unsupported instruction "
112 // Now, make a jmp instruction to the rest of the target function (minus the
114 // find address to jump to, relative to next address after jmp instruction
125 // jmp (Jump near, relative, displacement relative to next instruction)
137 // (Jump near, relative, displacement relative to next instruction)
140 // Find offset from instruction after jmp, to the replacement function.
151 // complete the jmp instruction
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  /external/dexmaker/
README 12 It has a small, close-to-the-metal API. This API mirrors the Dalvik bytecode specification giving you tight control over the bytecode emitted. Code is generated instruction-by-instruction; you bring your own abstract syntax tree if you need one. And since it uses Dalvik's dx tool as a backend, you get efficient register allocation and regular/wide instruction selection for free.
  /external/dexmaker/src/dx/java/com/android/dx/io/instructions/
FillArrayDataPayloadDecodedInstruction.java 20 * A decoded Dalvik instruction which contains the payload for
21 * a {@code packed-switch} instruction.
98 throw new UnsupportedOperationException("no index in instruction");
  /external/kernel-headers/original/asm-mips/
war.h 57 * - The `daddi' instruction fails to trap on overflow.
61 * - The `daddiu' instruction can produce an incorrect result.
91 * accessed for another instruction immeidately preceding when these
96 * instruction.
123 * by a load instruction to an uncached address to empty the response buffer."
132 * When an interrupt happens on a CP0 register read instruction, CPU may
183 * instruction
190 * Workaround: Execute a SYNC instruction after the cache instruction
201 * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued fo
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.h 1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
27 /// per-instruction flags. These must match the corresponding definitions in
31 // PPC970 Instruction Flags. These flags describe the characteristics of the
35 /// PPC970_First - This instruction starts a new dispatch group, so it will
39 /// PPC970_Single - This instruction starts a new dispatch group and
40 /// terminates it, so it will be the sole instruction in the group.
43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
48 /// an instruction is issued to.
53 /// These are the various PPC970 execution unit pipelines. Each instruction
55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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  /external/mesa3d/src/gallium/auxiliary/draw/
draw_pipe_aapoint.c 164 * TGSI instruction transform callback.
166 * Upon END instruction, insert texture sampling code for antialiasing.
176 /* emit our new declarations before the first instruction */
241 newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
242 newInst.Instruction.NumDstRegs = 1;
246 newInst.Instruction.NumSrcRegs = 2;
255 newInst.Instruction.Opcode = TGSI_OPCODE_ADD;
256 newInst.Instruction.NumDstRegs = 1;
260 newInst.Instruction.NumSrcRegs = 2;
272 newInst.Instruction.Opcode = TGSI_OPCODE_RSQ
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  /external/proguard/src/proguard/classfile/instruction/visitor/
InstructionVisitor.java 21 package proguard.classfile.instruction.visitor;
25 import proguard.classfile.instruction.*;
30 * <code>Instruction</code> objects.
  /external/proguard/src/proguard/classfile/visitor/
ExceptionHandlerFilter.java 30 * targets an instruction in the given range of offsets.
44 * @param startOffset the start of the instruction offset range.
45 * @param endOffset the end of the instruction offset range.
ExceptionRangeFilter.java 30 * overlaps with the given instruction range.
44 * @param startOffset the start offset of the instruction range.
45 * @param endOffset the end offset of the instruction range.

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