| /external/chromium_org/sdch/open-vcdiff/src/ |
| instruction_map.h | 36 // optimizes for fast encoding, that is, for taking a delta instruction
37 // inst (also known as instruction type), size, and mode and arriving at
44 // to create the instruction->opcode mappings. The caller *must* have
47 // max_mode is the maximum value for the mode of a COPY instruction.
55 // instruction and NOOP for its second instruction (or vice versa.)
74 // lookupFirstOpcode), finds an opcode that has the same first instruction as
76 // instruction.
128 // VCD_COPY being the last instruction type. The inst+mode values are:
143 // for each possible first instruction size (size1) in the code table
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| SsaInsn.java | 23 * An instruction in SSA form
188 * instruction, or null if no local variable assignment occurs. This
206 * used as sources for this instruction.
220 * @return {@code non-null;} a ROP representation of this instruction, with
241 * move-exception) instruction
248 * @return true if this is a move-exception instruction.
256 * @return true if this instruction can throw.
272 * Any non-phi move instruction
273 * @param insn {@code non-null;} the instruction to visit
279 * @param insn {@code non-null;} the instruction to visi
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| /external/llvm/lib/Transforms/Scalar/ |
| DeadStoreElimination.cpp | 104 /// DeleteDeadInstruction - Delete this instruction. Before we do, go through
105 /// and zero out all the operands of this instruction. If any of them become
110 static void DeleteDeadInstruction(Instruction *I,
114 SmallVector<Instruction*, 32> NowDeadInsts;
119 // Before we touch this instruction, remove it from memdep!
121 Instruction *DeadInst = NowDeadInsts.pop_back_val();
124 // This instruction is dead, zap it, in stages. Start by removing it from
136 if (Instruction *OpI = dyn_cast<Instruction>(Op))
148 /// hasMemoryWrite - Does this instruction write some memory? This only return
[all...] |
| /external/open-vcdiff/src/ |
| instruction_map.h | 36 // optimizes for fast encoding, that is, for taking a delta instruction
37 // inst (also known as instruction type), size, and mode and arriving at
44 // to create the instruction->opcode mappings. The caller *must* have
47 // max_mode is the maximum value for the mode of a COPY instruction.
55 // instruction and NOOP for its second instruction (or vice versa.)
74 // lookupFirstOpcode), finds an opcode that has the same first instruction as
76 // instruction.
128 // VCD_COPY being the last instruction type. The inst+mode values are:
143 // for each possible first instruction size (size1) in the code table
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| /dalvik/docs/ |
| dalvik-constraints.html | 201 The index of instruction <code>n+1</code> must equal the index of
202 instruction <code>n</code> plus the length of instruction
217 The last instruction in the <code>insns</code> array must end at index
247 All targets of a <code>packed-switch</code> instruction must be
263 All targets of a <code>sparse-switch</code> instruction must be
383 instruction must be a valid index into the method constant pool. The
400 instruction must be a valid index into the method constant pool.
450 instruction must be less than <code>256</code>.
464 The <code>new</code> instruction must not refer to array classes
[all...] |
| /dalvik/dx/src/com/android/dx/cf/code/ |
| BasicBlocker.java | 44 * middle of an instruction or is a definitely-dead opcode
56 * {@code non-null, sparse;} for each instruction offset to a branch of
57 * some sort, the list of targets for that instruction
62 * {@code non-null, sparse;} for each instruction offset to a throwing
63 * instruction, the list of exception handlers for that instruction
206 * possibility of throwing, so this instruction needs to
226 * only the jsr instruction) but is otherwise treated
228 * target and next instruction begin new blocks.)
285 * instruction at the end of this block, if any. I
[all...] |
| /external/chromium_org/third_party/mach_override/ |
| mach_override.c | 54 // Now the real jump instruction
73 // Now the real jump instruction
120 long instruction );
205 // Ensure first instruction isn't 'mfctr'.
254 // Build the branch absolute instruction to the escape island.
267 // Build the jump relative instruction to the escape island
296 // o Insert the original instruction into the reentry island.
297 // o Target the reentry island at the 2nd instruction of the
299 // o Replace the original instruction with the branch absolute.
311 // Someone replaced the instruction out from under us
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| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
159 /// such, whenever a client has an instance of instruction info, it should
164 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
165 /// extension instruction. That is, it's like a copy where it's legal for the
196 /// into the right format for a particular kind of LEA instruction. This may
202 /// operand to the LEA instruction.
210 /// may be able to convert a two-address instruction into a true
211 /// three-address instruction on demand. This allows the X86 target (for
216 /// performed, otherwise it returns the new instruction.
279 /// the specified stack slot into the specified machine instruction for th
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| /external/qemu/ |
| dis-asm.h | 4 The opcode library (libopcodes.a) provides instruction decoders for
5 a large variety of instruction sets, callable with an identical
6 interface, for making instruction-processing programs more independent
7 of the instruction set being processed. */
99 /* Nonzero if MACH has the v9 instruction set. */
237 dis_noninsn, /* Not a valid instruction */
238 dis_nonbranch, /* Not a branch instruction */
243 dis_dref, /* Data reference instruction */
244 dis_dref2 /* Two data references in instruction */
247 /* This struct is passed into the instruction decoding routine
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| /external/llvm/test/MC/AArch64/ |
| neon-diagnostics.s | 12 // CHECK-ERROR: error: invalid operand for instruction
15 // CHECK-ERROR: error: invalid operand for instruction
28 // CHECK-ERROR: error: invalid operand for instruction
31 // CHECK-ERROR: error: invalid operand for instruction
34 // CHECK-ERROR: error: invalid operand for instruction
46 // CHECK-ERROR: error: invalid operand for instruction
49 // CHECK-ERROR: error: invalid operand for instruction
60 // CHECK-ERROR: error: invalid operand for instruction
63 // CHECK-ERROR: error: invalid operand for instruction
81 // CHECK-ERROR: error: invalid operand for instruction
[all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | 38 // ConstantFold*Instruction Implementations
87 Instruction::CastOps firstOp = Instruction::CastOps(Op->getOpcode());
88 Instruction::CastOps secondOp = Instruction::CastOps(opc);
106 // the first element. If so, return the appropriate GEP instruction.
223 case Instruction::Or: {
238 case Instruction::And: {
252 case Instruction::LShr: {
274 case Instruction::Shl:
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| /art/runtime/ |
| disassembler.h | 34 // Dump a single instruction returning the length of that instruction.
|
| /dalvik/dx/tests/086-ssa-edge-split/ |
| Blort.java | 56 * Presently, any basic block ending in an instruction with
58 * only to the block between the switch instruction and the return
|
| /dalvik/vm/compiler/codegen/arm/ |
| README.txt | 36 - Factory.c (low-level routines for instruction selections)
37 - Gen.c (invoke the ISA-specific instruction selection routines)
|
| /dalvik/vm/compiler/template/mips/ |
| funopNarrower.S | 4 * that specifies an instruction that performs "result = op a0/a1", where
10 * (This would work for long-to-int, but that instruction is actually
|
| /dalvik/vm/mterp/armv5te/ |
| OP_CONST_CLASS.S | 16 GOTO_OPCODE(ip) @ jump to next instruction
35 GOTO_OPCODE(ip) @ jump to next instruction
|
| OP_CONST_STRING.S | 16 GOTO_OPCODE(ip) @ jump to next instruction
34 GOTO_OPCODE(ip) @ jump to next instruction
|
| OP_CONST_STRING_JUMBO.S | 18 GOTO_OPCODE(ip) @ jump to next instruction
36 GOTO_OPCODE(ip) @ jump to next instruction
|
| OP_PACKED_SWITCH.S | 4 * Handle a packed-switch or sparse-switch instruction. In both cases
35 GOTO_OPCODE(ip) @ jump to next instruction
|
| unopWider.S | 4 * that specifies an instruction that performs "result = op r0", where
20 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/mips/ |
| OP_PACKED_SWITCH.S | 4 * Handle a packed-switch or sparse-switch instruction. In both cases
34 GOTO_OPCODE(t0) # jump to next instruction
|
| binop.S | 4 * specifies an instruction that performs "result = a0 op a1".
5 * This could be a MIPS instruction or a function call. (If the result
|
| binop2addr.S | 4 * that specifies an instruction that performs "result = a0 op a1".
5 * This could be an MIPS instruction or a function call.
|
| binopLit16.S | 4 * that specifies an instruction that performs "result = a0 op a1".
5 * This could be an MIPS instruction or a function call. (If the result
|
| binopLit8.S | 4 * that specifies an instruction that performs "result = a0 op a1".
5 * This could be an MIPS instruction or a function call. (If the result
|
