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  /dalvik/vm/mterp/mips/
unflopWider.S 4 * that specifies an instruction that performs "result = op a0", where
32 GOTO_OPCODE(t0) # jump to next instruction
  /dalvik/vm/mterp/x86/
binop2addr.S 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an instruction or a function call.
  /external/chromium/sdch/open-vcdiff/src/
decodetable.h 71 // any pending second instruction or unread instruction will still be
84 // Returns the next instruction from the stream of opcodes,
89 // with the corresponding size for the returned instruction;
92 // If the instruction returned is VCD_COPY, *mode will
102 // Puts a single instruction back onto the front of the
103 // instruction stream. The next call to GetNextInstruction()
107 // only rewind one instruction.
  /external/chromium_org/sandbox/linux/seccomp-bpf/
basicblock.h 10 #include "sandbox/linux/seccomp-bpf/instruction.h"
39 std::vector<Instruction*> instructions;
  /external/chromium_org/sandbox/win/src/sidestep/
mini_disassembler_types.h 19 // This is not an instruction but a reference to another table
27 // A jump or call instruction
29 // A return instruction
31 // Any other type of instruction (in this case we don't care what it is)
61 AM_NOT_USED = 0, // This operand is not used for this instruction
169 // Table of instruction entries
182 // Is the operand encoded as bytes in the instruction (rather than
191 // in the instruction)?
  /external/chromium_org/sdch/open-vcdiff/src/
decodetable.h 71 // any pending second instruction or unread instruction will still be
84 // Returns the next instruction from the stream of opcodes,
89 // with the corresponding size for the returned instruction;
92 // If the instruction returned is VCD_COPY, *mode will
102 // Puts a single instruction back onto the front of the
103 // instruction stream. The next call to GetNextInstruction()
107 // only rewind one instruction.
  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
nomem64-err.errwarn 13 -:16: warning: `cdqe' is an instruction in 64-bit mode
14 -:17: warning: `swapgs' is an instruction in 64-bit mode
  /external/chromium_org/tools/memory_watcher/
mini_disassembler_types.h 21 // This is not an instruction but a reference to another table
29 // A jump or call instruction
31 // A return instruction
33 // Any other type of instruction (in this case we don't care what it is)
63 AM_NOT_USED = 0, // This operand is not used for this instruction
171 // Table of instruction entries
184 // Is the operand encoded as bytes in the instruction (rather than
193 // in the instruction)?
  /external/chromium_org/tools/traceline/traceline/sidestep/
mini_disassembler_types.h 19 // This is not an instruction but a reference to another table
27 // A jump or call instruction
29 // A return instruction
31 // Any other type of instruction (in this case we don't care what it is)
61 AM_NOT_USED = 0, // This operand is not used for this instruction
169 // Table of instruction entries
182 // Is the operand encoded as bytes in the instruction (rather than
191 // in the instruction)?
  /external/compiler-rt/lib/
clear_cache.c 20 * It is expected to invalidate the instruction cache for the
28 * Intel processors have a unified instruction and data cache
  /external/llvm/docs/HistoricalNotes/
2000-12-06-EncodingIdea.txt 6 Here's another idea with respect to keeping the common case instruction
9 Instead of encoding an instruction to operate on two register numbers,
2001-02-09-AdveComments.txt 1 Ok, here are my comments and suggestions about the LLVM instruction set.
8 essentially obvious from the instruction type, e.g., in br, it is obvious
16 (e.g., in the br instruction), it doesn't seem to help as much.
37 o There's a trade-off with the cast instruction:
39 valid for the operands of each instruction (you probably have thought
77 concern about an explicit 'icall' instruction?
91 .NET has a tailcall instruction?
101 instruction. (It could be optional so single-threaded codes are
  /external/llvm/include/llvm/IR/
Instruction.def 1 //===-- llvm/Instruction.def - File that describes Instructions -*- C++ -*-===//
161 HANDLE_OTHER_INST(45, ICmp , ICmpInst ) // Integer comparison instruction
163 HANDLE_OTHER_INST(47, PHI , PHINode ) // PHI node instruction
165 HANDLE_OTHER_INST(49, Select , SelectInst ) // select instruction
166 HANDLE_OTHER_INST(50, UserOp1, Instruction) // May be used internally in a pass
167 HANDLE_OTHER_INST(51, UserOp2, Instruction) // Internal to passes only
168 HANDLE_OTHER_INST(52, VAArg , VAArgInst ) // vaarg instruction
174 HANDLE_OTHER_INST(58, LandingPad, LandingPadInst) // Landing pad instruction.
  /external/llvm/include/llvm/MC/
MCCodeEmitter.h 1 //===-- llvm/MC/MCCodeEmitter.h - Instruction Encoding ----------*- C++ -*-===//
21 /// MCCodeEmitter - Generic instruction encoding interface.
MCFixup.h 1 //===-- llvm/MC/MCFixup.h - Instruction Relocation and Patching -*- C++ -*-===//
48 /// sequence (e.g., an encoded instruction) which requires assemble- or run-
51 /// Fixups are used any time the target instruction encoder needs to represent
52 /// some value in an instruction which is not yet concrete. The encoder will
53 /// encode the instruction assuming the value is 0, and emit a fixup which
64 /// an instruction or an assembler directive.
67 /// The byte index of start of the relocation inside the encoded instruction.
71 /// determine how the operand value should be encoded into the instruction.
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.h 1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
31 /// isLoadFromStackSlot - If the specified machine instruction is a direct
34 /// not, return 0. This predicate must return 0 if the instruction has
39 /// isStoreToStackSlot - If the specified machine instruction is a direct
42 /// not, return 0. This predicate must return 0 if the instruction has
75 /// non-NULL parameter, the last instruction is not emitted, but instead
92 /// For example, the following pseudo instruction
99 /// instruction between MTC1 and CVT_D32_W.
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.h 36 /// FCFID - The FCFID instruction, taking an f64 operand and producing
61 /// VPERM - The PPC VPERM Instruction.
78 /// This is basically a hard coded load instruction which additionally
86 /// a hard coded load instruction.
90 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
109 /// MTCTR instruction.
113 /// BCTRL instruction.
119 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
181 /// TLS model, produces an ADDIS8 instruction that adds the GO
    [all...]
  /external/llvm/lib/Transforms/Scalar/
EarlyCSE.cpp 50 Instruction *Inst;
52 SimpleValue(Instruction *I) : Inst(I) {
57 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() ||
58 Inst == DenseMapInfo<Instruction*>::getTombstoneKey();
61 static bool canHandle(Instruction *Inst) {
82 return DenseMapInfo<Instruction*>::getEmptyKey();
85 return DenseMapInfo<Instruction*>::getTombstoneKey();
93 Instruction *Inst = Val.Inst;
138 isa<ShuffleVectorInst>(Inst)) && "Invalid/unknown instruction");
147 Instruction *LHSI = LHS.Inst, *RHSI = RHS.Inst
    [all...]
  /external/llvm/test/CodeGen/Generic/
fwdtwice.ll 9 ;; register argument of the "branch-on-register" instruction, i.e.,
11 ;; This produces the bogus output instruction:
  /external/llvm/test/CodeGen/R600/
bfe_uint.ll 13 ; This program could be implemented using a BFE_UINT instruction, however
15 ; implmented with a LSHR instruction, which is better, because LSHR has less
  /external/llvm/test/MC/X86/AlignedBundling/
long-nop-pad.s 10 # This callq instruction is 5 bytes long
19 # This push instruction is 1 byte long
  /external/open-vcdiff/src/
decodetable.h 71 // any pending second instruction or unread instruction will still be
84 // Returns the next instruction from the stream of opcodes,
89 // with the corresponding size for the returned instruction;
92 // If the instruction returned is VCD_COPY, *mode will
102 // Puts a single instruction back onto the front of the
103 // instruction stream. The next call to GetNextInstruction()
107 // only rewind one instruction.
  /external/proguard/src/proguard/classfile/instruction/visitor/
AllInstructionVisitor.java 21 package proguard.classfile.instruction.visitor;
29 * This AttributeVisitor lets a given InstructionVisitor visit all Instruction
  /external/proguard/src/proguard/evaluation/
BranchUnit.java 34 * Sets the new instruction offset.
43 * Sets the new instruction offset, depending on the certainty of the
  /external/proguard/src/proguard/optimize/info/
SideEffectInstructionChecker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
33 * This class can tell whether an instruction has any side effects. Return
59 public boolean hasSideEffects(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
63 instruction.accept(clazz, method, codeAttribute, offset, this);
71 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}

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