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  /external/llvm/include/llvm/CodeGen/
TargetSchedule.h 31 /// Provide an instruction scheduling machine model to CodeGen passes.
46 /// \brief Initialize the machine model for instruction scheduling.
54 /// Return the MCSchedClassDesc for this instruction.
60 /// \brief Return true if this machine model includes an instruction-level
149 /// \brief Compute the instruction latency based on the available machine
152 /// Compute and return the expected latency of this instruction independent of
154 /// occasionally useful to help estimate instruction cost.
  /external/llvm/include/llvm/MC/
MCAsmBackend.h 123 /// mayNeedRelaxation - Check whether the given instruction may need
126 /// \param Inst - The instruction to test.
130 /// fixup requires the associated instruction to be relaxed.
136 /// RelaxInstruction - Relax the instruction in the given fragment to the next
137 /// wider instruction.
139 /// \param Inst The instruction to relax, which may be the same as the
141 /// \param [out] Res On return, the relaxed instruction.
MCTargetAsmParser.h 115 /// ParseInstruction - Parse one assembly instruction.
117 /// The parser is positioned following the instruction name. The target
118 /// specific instruction parser should parse the entire instruction and
123 /// \param Name - The instruction name.
149 /// instruction as an actual MCInst and emit it to the specified MCStreamer.
169 /// checkTargetMatchPredicate - Validate the instruction match against
  /external/llvm/lib/Analysis/
MemDepPrinter.cpp 37 typedef PointerIntPair<const Instruction *, 2, DepType> InstTypePair;
40 typedef DenseMap<const Instruction *, DepSet> DepSetMap;
74 static InstTypePair getInstTypePair(const Instruction* inst, DepType type) {
102 Instruction *Inst = &*I;
145 llvm_unreachable("Unknown memory instruction!");
162 const Instruction *Inst = &*I;
172 const Instruction *DepInst = I->first.getPointer();
  /external/llvm/lib/CodeGen/
RegisterCoalescer.h 27 /// instruction would become an identity copy after coalescing.
53 /// copy instruction.
73 /// setRegisters - set registers to match the copy instruction MI. Return
74 /// false if MI is not a coalescable copy instruction.
81 /// isCoalescable - Return true if MI is a copy instruction that will become
88 /// isPartial - Return true if the original copy instruction did not copy
97 /// the original copy instruction.
  /external/llvm/lib/ExecutionEngine/Interpreter/
Execution.cpp 10 // This file contains the actual instruction interpreter.
45 // Binary Instruction Implementations
59 dbgs() << "Unhandled type for FAdd instruction: " << *Ty << "\n";
70 dbgs() << "Unhandled type for FSub instruction: " << *Ty << "\n";
81 dbgs() << "Unhandled type for FMul instruction: " << *Ty << "\n";
92 dbgs() << "Unhandled type for FDiv instruction: " << *Ty << "\n";
107 dbgs() << "Unhandled type for Rem instruction: " << *Ty << "\n";
331 dbgs() << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n";
387 dbgs() << "Unhandled type for FCmp NE instruction: " << *Ty << "\n";
407 dbgs() << "Unhandled type for FCmp LE instruction: " << *Ty << "\n"
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonCopyToCombine.cpp 12 // replace them with a combine instruction.
119 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
170 /// areCombinableOperations - Returns true if the two instruction can be merge
221 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
260 // If I2 kills its operand and we move I2 over an instruction that also
261 // uses I2's use reg we need to modify that (first) instruction to now kill
269 // If the intervening instruction I:
286 // Update the intermediate instruction to with the kill flag.
307 // Track killed operands. If we move across an instruction that kills ou
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  /external/llvm/lib/Target/Mips/
MipsAnalyzeImmediate.cpp 17 // Add I to the instruction sequences.
19 // Add an instruction seqeunce consisting of just I.
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
99 // Replace the first instruction and erase the second.
107 // The length of an instruction sequence is at most 7.
143 // Get the list of instruction sequences.
149 // Set Insts to the shortest instruction sequence.
  /external/llvm/lib/Target/X86/Disassembler/
X86Disassembler.h 11 // 64-bit X86 instruction sets. The main decode sequence for an assembly
12 // instruction in this disassembler is:
14 // 1. Read the prefix bytes and determine the attributes of the instruction.
39 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
45 // instruction; the type indicates how to interpret the value once it has
52 // 7. As the last step, the disassembler translates the instruction information
57 // emits the instruction decode tables discussed above during compilation, and
  /external/llvm/lib/Transforms/Scalar/
LoopRotation.cpp 45 // LCSSA form makes instruction renaming easier.
100 /// these instruction that were outside of the loop, we have to insert PHI nodes
129 // Visit each use of the OrigHeader instruction.
140 Instruction *UserInst = cast<Instruction>(U.getUser());
165 /// heuristics. We handle a single arithmetic instruction along with any type
181 case Instruction::GetElementPtr:
186 case Instruction::Add:
187 case Instruction::Sub:
188 case Instruction::And
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Reg2Mem.cpp 48 bool valueEscapes(const Instruction *Inst) const {
52 const Instruction *I = cast<Instruction>(*UI);
79 // Find first non-alloca instruction and create insertion point. This is
92 std::list<Instruction*> WorkList;
105 for (std::list<Instruction*>::iterator ilb = WorkList.begin(),
121 for (std::list<Instruction*>::iterator ilb = WorkList.begin(),
  /external/open-vcdiff/src/
codetable.h 29 // The instruction types from section 5.5 (mistakenly labeled 5.4) of the RFC.
37 // The following values are not true instruction types, but rather
55 // as described in Section 7 of RFC 3284. Each instruction code
61 // the size will be encoded separately from the instruction code, as a Varint
84 // max_mode is the maximum value for the mode of a COPY instruction;
94 // (Instruction Codes), which contains the following specification:
96 // Each instruction code entry contains six fields, each of which is a single
  /external/oprofile/events/ppc/7450/
events 12 event:0xe counters:0,1 um:zero minimum:3000 name:VPU_CYCLES : Cycles a VPU Instruction
13 event:0xf counters:0,1 um:zero minimum:3000 name:VFPU_CYCLES : Cycles a VFPU Instruction
14 event:0x10 counters:0,1 um:zero minimum:3000 name:VIU1_CYCLES : Cycles a VIU1 Instruction
15 event:0x11 counters:0,1 um:zero minimum:3000 name:VIU2_CYCLES : Cycles a VIU2 Instruction
18 event:0x15 counters:0,1 um:zero minimum:3000 name:L1_ICACHE_MISSES : L1 Instruction Cache Misses
25 event:0x29 counters:0 um:zero minimum:3000 name:L1_ICACHE_ACCESSES : L1 Instruction Cache Accesses
26 event:0x2a counters:0 um:zero minimum:3000 name:INSN_BP_MATCHES : Instruction Breakpoint Matches
  /ndk/docs/text/
CPU-FEATURES.text 59 > Indicates that the device's CPU supports VFPv2 instruction set.
63 > Indicates that the device's CPU supports the ARMv7-A instruction
69 instruction set extension. Due to the definition of 'armeabi-v7a',
83 (a.k.a. NEON) vector instruction set extension. Note that ARM
121 > Indicates that the device's CPU supports the SSSE3 instruction
126 > Indicates that the device's CPU supports the POPCNT instruction.
129 > Indicates that the device's CPU supports the MOVBE instruction.
  /frameworks/compile/slang/BitWriter_2_9/
BitcodeWriter.cpp 80 default: llvm_unreachable("Unknown cast instruction!");
81 case Instruction::Trunc : return bitc::CAST_TRUNC;
82 case Instruction::ZExt : return bitc::CAST_ZEXT;
83 case Instruction::SExt : return bitc::CAST_SEXT;
84 case Instruction::FPToUI : return bitc::CAST_FPTOUI;
85 case Instruction::FPToSI : return bitc::CAST_FPTOSI;
86 case Instruction::UIToFP : return bitc::CAST_UITOFP;
87 case Instruction::SIToFP : return bitc::CAST_SITOFP;
88 case Instruction::FPTrunc : return bitc::CAST_FPTRUNC;
89 case Instruction::FPExt : return bitc::CAST_FPEXT
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  /dalvik/dexgen/src/com/android/dexgen/rop/code/
BasicBlock.java 90 "instruction");
149 * @return {@code non-null;} the instruction list
195 * Gets the first instruction of this block. This is just a
198 * @return {@code non-null;} the first instruction
205 * Gets the last instruction of this block. This is just a
208 * @return {@code non-null;} the last instruction
227 * This is just a shorthand for inspecting the last instruction in
242 * instruction in the block to see if it could throw, and if so,
256 * the registers in each instruction are offset by the given
  /dalvik/dx/src/com/android/dx/rop/code/
BasicBlock.java 90 "instruction");
149 * @return {@code non-null;} the instruction list
195 * Gets the first instruction of this block. This is just a
198 * @return {@code non-null;} the first instruction
205 * Gets the last instruction of this block. This is just a
208 * @return {@code non-null;} the last instruction
227 * This is just a shorthand for inspecting the last instruction in
242 * instruction in the block to see if it could throw, and if so,
256 * the registers in each instruction are offset by the given
  /external/chromium_org/third_party/tcmalloc/chromium/src/windows/
mini_disassembler_types.h 48 // This is not an instruction but a reference to another table
56 // A jump or call instruction
58 // A return instruction
60 // Any other type of instruction (in this case we don't care what it is)
90 AM_NOT_USED = 0, // This operand is not used for this instruction
149 // defines MOV as the only instruction supporting a 64-bit immediate operand.
208 // Table of instruction entries
221 // Is the operand encoded as bytes in the instruction (rather than
230 // in the instruction)?
  /external/chromium_org/third_party/tcmalloc/vendor/src/windows/
mini_disassembler_types.h 48 // This is not an instruction but a reference to another table
56 // A jump or call instruction
58 // A return instruction
60 // Any other type of instruction (in this case we don't care what it is)
90 AM_NOT_USED = 0, // This operand is not used for this instruction
149 // defines MOV as the only instruction supporting a 64-bit immediate operand.
208 // Table of instruction entries
221 // Is the operand encoded as bytes in the instruction (rather than
230 // in the instruction)?
  /external/dexmaker/src/dx/java/com/android/dx/rop/code/
BasicBlock.java 90 "instruction");
149 * @return {@code non-null;} the instruction list
195 * Gets the first instruction of this block. This is just a
198 * @return {@code non-null;} the first instruction
205 * Gets the last instruction of this block. This is just a
208 * @return {@code non-null;} the last instruction
227 * This is just a shorthand for inspecting the last instruction in
242 * instruction in the block to see if it could throw, and if so,
256 * the registers in each instruction are offset by the given
  /external/llvm/include/llvm/Analysis/
SparsePropagation.h 27 class Instruction;
101 /// ComputeInstructionState - Given an instruction and a vector of its operand
102 /// values, compute the result value of the instruction.
103 virtual LatticeVal ComputeInstructionState(Instruction &I, SparseSolver &SS) {
125 std::vector<Instruction*> InstWorkList; // Worklist of insts to process.
181 /// UpdateState - When the state for some instruction is potentially updated,
183 void UpdateState(Instruction &Inst, LatticeVal V);
194 /// successors are reachable from a given terminator instruction.
198 void visitInst(Instruction &I);
  /external/llvm/lib/DebugInfo/
DWARFDebugLine.h 48 // The size in bytes of the smallest target machine instruction. Statement
98 // The program-counter value corresponding to a machine instruction
103 // instruction cannot be attributed to any source line.
110 // corresponding to a machine instruction.
112 // An unsigned integer whose value encodes the applicable instruction set
113 // architecture for the current instruction.
115 // A boolean indicating that the current instruction is the beginning of a
118 // A boolean indicating that the current instruction is the
137 // guaranteed to be in the order of ascending instruction address.
  /external/llvm/lib/Transforms/InstCombine/
InstCombineLoadStoreAlloca.cpp 33 if (CE->getOpcode() == Instruction::BitCast ||
34 CE->getOpcode() == Instruction::GetElementPtr)
48 SmallVectorImpl<Instruction *> &ToDelete,
55 User *U = cast<Instruction>(*UI);
135 // Otherwise, the transform is safe. Remember the copy instruction.
146 SmallVectorImpl<Instruction *> &ToDelete) {
153 Instruction *InstCombiner::visitAllocaInst(AllocaInst &AI) {
181 // insert our getelementptr instruction...
187 Instruction *GEP =
216 // Get the first instruction in the entry block
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  /external/llvm/lib/Transforms/Utils/
BasicBlockUtils.cpp 49 Instruction &I = BB->back();
50 // If this instruction is used, replace uses with an arbitrary value.
194 /// ReplaceInstWithValue - Replace all uses of an instruction (specified by BI)
195 /// with a value, then remove and delete the original instruction.
199 Instruction &I = *BI;
200 // Replaces all of the uses of the instruction with uses of the value
207 // Delete the unnecessary instruction now...
212 /// ReplaceInstWithInst - Replace the instruction specified by BI with the
213 /// instruction specified by I. The original instruction is deleted and BI i
    [all...]
  /external/llvm/utils/TableGen/
DAGISelEmitter.cpp 1 //===- DAGISelEmitter.cpp - Generate an instruction selector --------------===//
10 // This tablegen backend emits a DAG instruction selector.
23 /// and emission of the instruction selector.
37 /// This is a temporary hack. We should really include the instruction
45 if (Op->isSubClassOf("Instruction")) {
64 if (Op->isSubClassOf("Instruction")) {
102 // If the patterns have equal complexity, compare generated instruction cost
123 emitSourceFileHeader("DAG Instruction Selector for the " +
127 << "// *** instruction selector class. These functions are really "

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