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  /dalvik/vm/mterp/mips/
OP_IPUT_OBJECT_QUICK.S 21 GOTO_OPCODE(t0) # jump to next instruction
OP_IPUT_WIDE_QUICK.S 16 GOTO_OPCODE(t0) # jump to next instruction
OP_MUL_LONG_2ADDR.S 27 GOTO_OPCODE(t1) # jump to next instruction
  /dalvik/vm/mterp/x86/
OP_PACKED_SWITCH.S 4 * Handle a packed-switch or sparse-switch instruction. In both cases
entry.S 52 /* Fetch next instruction before potential jump */
61 /* Normal case: start executing the instruction at rPC */
71 * last instruction causes us to return to whoever called dvmMterpStdRun.
103 GOTO_NEXT_R %ecx # start executing the instruction at rPC
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/
r300_vs_draw.c 70 /* First instruction processed? */
72 /* End instruction processed? */
246 if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
249 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
250 new_inst.Instruction.NumDstRegs = 1;
254 new_inst.Instruction.NumSrcRegs = 1;
261 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
262 new_inst.Instruction.NumDstRegs = 1;
266 new_inst.Instruction.NumSrcRegs = 1;
273 /* Not an END instruction. *
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  /external/chromium_org/v8/src/x64/
cpu-x64.cc 55 // No need to flush the instruction cache on Intel. On Intel instruction
59 // own instruction cache updated automatically.
61 // If flushing of the instruction cache becomes necessary Windows has the
  /external/clang/test/CodeGen/
branch-target-layout.c 10 // order of a branch instruction's labels cannot be used as a source order bias.
linetable-endscope.c 3 // Check the line numbers for the ret instruction. We expect it to be
  /external/dexmaker/src/dx/java/com/android/dx/dex/code/
HighRegisterPrefix.java 26 * Combination instruction which turns into a variable number of
29 * in translating an instruction whose register requirements cannot
135 * Returns the proper move instruction for the given source spec
140 * @return {@code non-null;} the appropriate move instruction
  /external/kernel-headers/original/asm-arm/
mtd-xip.h 23 /* fill instruction prefetch */
  /external/kernel-headers/original/asm-mips/
sgidefs.h 24 * With the introduction of MIPS32 / MIPS64 instruction sets definitions
  /external/llvm/examples/ModuleMaker/
ModuleMaker.cpp 48 // Create the add instruction... does not insert...
49 Instruction *Add = BinaryOperator::Create(Instruction::Add, Two, Three,
55 // Create the return instruction and add it to the basic block
  /external/llvm/include/llvm/Analysis/
CFG.h 26 class Instruction;
41 /// in the terminator instruction's list of successors. It is an error to call
64 bool isPotentiallyReachable(const Instruction *From, const Instruction *To,
  /external/llvm/lib/Analysis/
InstCount.cpp 33 #include "llvm/IR/Instruction.def"
46 #include "llvm/IR/Instruction.def"
48 void visitInstruction(Instruction &I) {
49 errs() << "Instruction Count does not know about " << I;
  /external/llvm/lib/CodeGen/
MachineLICM.cpp 19 // constructs that are not exposed before lowering and instruction selection.
164 /// HoistPostRA - When an instruction is found to only use loop invariant
165 /// operands that is safe to hoist, this instruction is called to do the
169 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
181 /// IsLICMCandidate - Returns true if the instruction may be a suitable
182 /// candidate for LICM. e.g. If the instruction is a call, then it's
186 /// IsLoopInvariantInst - Returns true if the instruction is loop
189 /// and the instruction is hoistable.
193 /// HasLoopPHIUse - Return true if the specified instruction is used by any
206 /// check if hoisting an instruction of the given cost matrix can cause hig
    [all...]
PeepholeOptimizer.cpp 30 // If the "sub" instruction all ready sets (or could be modified to set) the
31 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
32 // eliminate the "cmp" instruction.
40 // If the branch instruction can use flag from "sub", then we can replace
41 // "sub" with "subs" and eliminate the "cmp" instruction.
54 // Loads that can be folded into a later instruction. A load is foldable
138 /// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
185 // Uses that are in the same BB of uses of the result of the instruction.
188 // Uses that the result of the instruction can reach
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  /external/llvm/lib/IR/
CMakeLists.txt 20 Instruction.cpp
  /external/llvm/lib/MC/
MCCodeEmitter.cpp 1 //===-- MCCodeEmitter.cpp - Instruction Encoding --------------------------===//
  /external/llvm/lib/Target/Hexagon/
HexagonRemoveSZExtArgs.cpp 62 for (Instruction::use_iterator UI = Arg->use_begin();
65 Instruction* Use = cast<Instruction>(*UI);
71 Instruction* First = F.getEntryBlock().begin();
  /external/llvm/lib/Target/X86/Disassembler/
X86DisassemblerDecoder.h 11 * It contains the public interface of the instruction decoder.
35 * Accessor functions for various fields of an Intel instruction
465 * the decoder. Reads a single byte from the instruction's address space.
470 * @param address - The address in the instruction's address space that should
487 * The x86 internal instruction, which is produced by the decoder.
502 /* General instruction information */
506 /* The start of the instruction, usable with the reader */
508 /* The length of the instruction, in bytes */
537 /* Offsets from the start of the instruction to the pieces of data, which is
550 /* The ModR/M byte of the instruction, if it is an opcode extension *
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  /external/llvm/test/CodeGen/ARM/
2011-08-12-vmovqqqq-pseudo.ll 2 ; Make sure that the VMOVQQQQ pseudo instruction is handled properly
2012-10-04-LDRB_POST_IMM-Crash.ll 2 ; Check that LDRB_POST_IMM instruction emitted properly.
peephole-bitcast.ll 8 ; Peephole leaves a dead vmovsr instruction behind, and depends on linear scan
twoaddrinstr.ll 1 ; Tests for the two-address instruction pass.

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