| /external/llvm/test/CodeGen/Hexagon/ |
| fusedandshift.ll | 2 ; Check that we generate fused logical and with shift instruction.
|
| /external/llvm/test/CodeGen/R600/ |
| icmp-select-sete-reverse-args.ll | 4 ;to a SETNE_INT. There should only be one SETNE_INT instruction.
|
| legalizedag-bug-expand-setcc.ll | 7 ; This bug caused the icmp IR instruction to be expanded to two machine
|
| selectcc-icmp-select-float.ll | 4 ; CND* instruction.
|
| vtx-schedule.ll | 4 ; the result of another VTX_READ instruction were being grouped in the
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-bcc.ll | 3 ; generation, so use memory barrier instruction to make sure it doesn't
|
| /external/llvm/test/CodeGen/X86/ |
| 2003-08-03-CallArgLiveRanges.ll | 2 ; The old instruction selector used to load all arguments to a call up in
|
| ga-offset.ll | 10 ; This store should fold to a single mov instruction.
|
| hoist-common.ll | 3 ; Common "xorb al, al" instruction in the two successor blocks should be
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| ldp-postind.predictable.txt | 5 # CHECK-NOT: potentially undefined instruction encoding
|
| ldp-preind.predictable.txt | 5 # CHECK-NOT: potentially undefined instruction encoding
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-IT-CC15.txt | 12 # printing the final instruction in this list.
|
| /external/llvm/test/MC/ELF/ |
| relax-all-flag.s | 4 // expect to see a different instruction.
|
| /external/llvm/test/MC/MachO/ARM/ |
| thumb-bl-jbits.s | 15 # We are checking that the branch and link instruction which is:
|
| /external/llvm/test/Other/ |
| 2002-02-24-InlineBrokePHINodes.ll | 2 ; when a node is split around the call instruction. The verifier caught the error.
|
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_vs_draw.c | 70 /* First instruction processed? */
72 /* End instruction processed? */
246 if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
249 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
250 new_inst.Instruction.NumDstRegs = 1;
254 new_inst.Instruction.NumSrcRegs = 1;
261 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
262 new_inst.Instruction.NumDstRegs = 1;
266 new_inst.Instruction.NumSrcRegs = 1;
273 /* Not an END instruction. *
[all...] |
| /external/oprofile/daemon/ |
| opd_ibs_trans.h | 3 * AMD Family10h Instruction Based Sampling (IBS) translation.
|
| /external/oprofile/events/arm/armv6/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
8 event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
|
| /external/oprofile/events/arm/armv7-common/ |
| events | 5 event:0x01 counters:1,2,3,4,5,6 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
6 event:0x02 counters:1,2,3,4,5,6 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
15 event:0x0B counters:1,2,3,4,5,6 um:zero minimum:500 name:CID_WRITE : Instruction that writes to the Context ID Register architecturally executed
17 event:0x0D counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_IMM_BRANCH : Immediate branch instruction executed (taken or not)
|
| /external/oprofile/events/arm/xscale1/ |
| events | 3 event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
8 event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
10 event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instruction executed
|
| /external/oprofile/events/arm/xscale2/ |
| events | 3 event:0x00 counters:1,2,3,4 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
8 event:0x05 counters:1,2,3,4 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
10 event:0x07 counters:1,2,3,4 um:zero minimum:500 name:INSN_EXECUTED : instruction executed
|
| /external/oprofile/events/avr32/ |
| events | 3 event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction TLB misses
8 event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
|
| /external/proguard/src/proguard/optimize/info/ |
| AccessMethodMarker.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
50 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
|
| ReadWriteFieldMarker.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
50 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
|
| /external/qemu/ |
| gen-icount.h | 3 /* Helpers for instruction counting code generation. */
|
