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  /external/kernel-headers/original/asm-arm/
byteorder.h 7 * and word accesses (data or instruction) appear as:
12 * and word accesses (data or instruction) appear as:
  /external/llvm/docs/HistoricalNotes/
2001-07-06-LoweringIRForCodeGen.txt 8 move-conditional instruction. I don't think we want to put that in the core
10 conditional move instruction in the VM, it is pretty difficult to maintain a
  /external/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 90 // Set up the instruction printer.
147 // LLVMDisasmInstruction() disassembles a single instruction using the
149 // instruction are specified in the parameter Bytes, and contains at least
150 // BytesSize number of bytes. The instruction is at the address specified by
151 // the PC parameter. If a valid instruction can be disassembled its string is
154 // instruction or zero if there was no valid instruction. If this function
221 // Try to set up the new instruction printer.
  /external/llvm/lib/Transforms/Instrumentation/
BoundsChecking.cpp 60 Instruction *Inst;
99 /// emitBranchToTrap - emit a branch instruction to a trap block.
113 Instruction *Inst = Builder->GetInsertPoint();
179 // check HANDLE_MEMORY_INST in include/llvm/Instruction.def for memory
181 std::vector<Instruction*> WorkList;
183 Instruction *I = &*i;
190 for (std::vector<Instruction*>::iterator i = WorkList.begin(),
204 llvm_unreachable("unknown Instruction type");
  /external/llvm/test/CodeGen/AArch64/
regress-tblgen-chains.ll 4 ; instruction as needing a chain on its own account if it had a built-in pattern
7 ; LS8_LDR instruction (same operands other than the non-existent chain) and the
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_parse.c 187 copy_token(&inst->Instruction, &token);
189 if (inst->Instruction.Predicate) {
193 if (inst->Instruction.Label) {
197 if (inst->Instruction.Texture) {
204 assert( inst->Instruction.NumDstRegs <= TGSI_FULL_MAX_DST_REGISTERS );
206 for( i = 0; i < inst->Instruction.NumDstRegs; i++ ) {
239 assert( inst->Instruction.NumSrcRegs <= TGSI_FULL_MAX_SRC_REGISTERS );
241 for( i = 0; i < inst->Instruction.NumSrcRegs; i++ ) {
  /external/oprofile/events/mips/vr5432/
events 9 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
13 event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
  /external/proguard/src/proguard/classfile/visitor/
ExceptionExcludedOffsetFilter.java 30 * does not cover the instruction at the given offset.
43 * @param instructionOffset the instruction offset.
ExceptionOffsetFilter.java 30 * covers the instruction at the given offset.
43 * @param instructionOffset the instruction offset.
  /external/proguard/src/proguard/evaluation/
InvocationUnit.java 25 import proguard.classfile.instruction.ConstantInstruction;
54 * field or method reference instruction.
  /dalvik/vm/mterp/out/
InterpAsm-armv7-a-neon.S 67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
71 one instruction to make instruction-counting easier. They MUST NOT alter
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
165 * Put the instruction's opcode field into the specified register
    [all...]
InterpAsm-armv7-a.S 67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
71 one instruction to make instruction-counting easier. They MUST NOT alter
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
165 * Put the instruction's opcode field into the specified register
    [all...]
InterpAsm-armv5te-vfp.S 67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
71 one instruction to make instruction-counting easier. They MUST NOT alter
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
165 * Put the instruction's opcode field into the specified register
    [all...]
  /external/llvm/lib/Transforms/Scalar/
LoopIdiomRecognize.cpp 74 /// (aka goto instruction).
119 /// is set to the instruction counting the pupulation bit. 2) \p CntPhi
123 (Instruction *&CntInst, PHINode *&CntPhi, Value *&Var) const;
126 void transform (Instruction *CntInst, PHINode *CntPhi, Value *Var);
155 Value *SplatValue, Instruction *TheStore,
227 /// deleteDeadInstruction - Delete this instruction. Before we do, go through
228 /// and zero out all the operands of this instruction. If any of them become
231 static void deleteDeadInstruction(Instruction *I, ScalarEvolution &SE,
233 SmallVector<Instruction*, 32> NowDeadInsts;
237 // Before we touch this instruction, remove it from SE
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 9 // Vector, Reduction, and Cube instructions need to fill the entire instruction
11 // into several instructions that will completely fill the instruction group.
70 // Expand the instruction
122 // Mask the write if the original instruction does not write to
132 // Add the new instruction
143 assert(!"Unknown CUBE instruction");
R600InstrInfo.h 1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
54 /// instruction slots within an instruction group.
113 ///hasFlagOperand - Returns true if this instruction has an operand for
123 ///getFlagOp - Return the operand containing the flags for this instruction.
126 ///clearFlag - Clear the specified flag on the instruction.
  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
ssse3.c 175 #define CHECK_FUNCTION(instruction, extension, additionnal, pDst, pSrc) \
182 test_##instruction##_c( pDst, pSrc, additionnal ); \
183 test_##instruction##_##extension( temp_dst, temp_src ); \
187 #define CHECK_FUNCTIONS(instruction) \
188 CHECK_FUNCTION(instruction, mmx, 0, pDst, pSrc); \
189 CHECK_FUNCTION(instruction, xmm, 1, pDst, pSrc)
  /external/kernel-headers/original/asm-x86/
alternative_32.h 9 u8 *instr; /* original instruction */
12 u8 instrlen; /* length of original instruction */
13 u8 replacementlen; /* length of new instruction, <= instrlen */
52 " .long 663f\n" /* new instruction */ \
76 " .long 663f\n" /* new instruction */ \
91 " .long 663f\n" /* new instruction */ \
  /external/llvm/include/llvm/Analysis/
ConstantFolding.h 26 class Instruction;
34 /// ConstantFoldInstruction - Try to constant fold the specified instruction.
39 Constant *ConstantFoldInstruction(Instruction *I, const DataLayout *TD = 0,
49 /// ConstantFoldInstOperands - Attempt to constant fold an instruction with the
61 /// instruction (icmp/fcmp) with the specified operands. If it fails, it
70 /// instruction with the specified operands and indices. The constant result is
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
57 /// insertNoop - Insert a noop into the instruction stream at the specified
67 /// count as an instruction.
68 /// Any other non-whitespace text is considered an instruction, with
95 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
123 // No idea how to commute this instruction. Target should implement its own.
158 // Create a new instruction.
177 /// operand indices that would swap value. Return true if the instruction
300 "Instruction cannot be duplicated");
304 // If the COPY instruction in MI can be folded to a stack operation, retur
    [all...]
  /external/llvm/lib/IR/
TypeFinder.cpp 56 const Instruction &I = *II;
58 // Incorporate the type of the instruction.
61 // Incorporate non-instruction operand types. (We are incorporating all
65 if (!isa<Instruction>(OI))
126 // If this is an instruction, we incorporate it separately.
127 if (isa<Instruction>(V))
  /external/llvm/lib/MC/
MCExternalSymbolizer.cpp 21 // the caller. If the instruction is a branch instruction then IsBranch is true,
24 // symbolic information at the Address for this instruction. If that returns
128 // instruction with the base register that is the Pc. These can often be values
129 // in a literal pool near the Address of the instruction. The Address of the
130 // instruction and its immediate Value are used as a possible literal pool entry.
  /external/llvm/lib/Transforms/Utils/
SimplifyInstructions.cpp 11 // The analysis is applied to every instruction, and if it simplifies then the
12 // instruction is replaced by the simplification. If you are looking for a pass
13 // that performs serious instruction folding, use the instcombine pass instead.
51 SmallPtrSet<const Instruction*, 8> S1, S2, *ToSimplify = &S1, *Next = &S2;
58 Instruction *I = BI++;
70 Next->insert(cast<Instruction>(*UI));
  /external/llvm/test/TableGen/
TargetInstrInfo.td 7 class Instruction { // Would have other stuff eventually
61 Format f, list<dag> rtl> : Instruction {
70 // Start of instruction definitions, the real point of this file.
80 // 4. We capture the behavior of the instruction with a simplified RTL-like
86 // Simple copy instruction.
121 // Alternatively, if each tmporary register is only used once, the instruction
  /external/mesa3d/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 9 // Vector, Reduction, and Cube instructions need to fill the entire instruction
11 // into several instructions that will completely fill the instruction group.
70 // Expand the instruction
122 // Mask the write if the original instruction does not write to
132 // Add the new instruction
143 assert(!"Unknown CUBE instruction");

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