| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 51 /// Create a MachineInstrBuilder for manipulating an existing instruction.
55 /// Allow automatic conversion to the machine instruction we are working on.
220 /// BuildMI - Builder interface. Specify how to create the initial instruction
241 /// instruction before the given position in the given MachineBasicBlock, and
281 /// instruction before the given position in the given MachineBasicBlock, and
318 /// instruction at the end of the given MachineBasicBlock, and does NOT take a
328 /// instruction at the end of the given MachineBasicBlock, and sets up the first
418 /// BB above the bundle or instruction at Pos.
437 /// Create an MIBundleBuilder representing an existing instruction or bundle
449 /// Return an iterator to the first bundled instruction
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 221 /// instruction info tracks.
284 /// lower 16 bit of the address. Used only via movw instruction.
288 /// higher 16 bit of the address. Used only via movt instruction.
294 /// Used only via movw instruction.
299 /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
305 /// Used only via movw instruction.
311 /// Used only via movt instruction.
321 // Instruction Flags.
334 // Instruction encoding formats.
407 // UnaryDP - Indicates this is a unary data processing instruction, i.e
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXGenericToNVVM.cpp | 306 // If any of the operands has been modified, construct the instruction with
310 case Instruction::ICmp:
314 case Instruction::FCmp:
319 case Instruction::ExtractElement:
322 case Instruction::InsertElement:
326 case Instruction::ShuffleVector:
330 case Instruction::ExtractValue:
333 case Instruction::InsertValue:
337 case Instruction::GetElementPtr:
346 case Instruction::Select
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_sanity.c | 317 if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
324 info = tgsi_get_opcode_info( inst->Instruction.Opcode );
326 report_error( ctx, "(%u): Invalid instruction opcode", inst->Instruction.Opcode );
330 if (info->num_dst != inst->Instruction.NumDstRegs) {
333 if (info->num_src != inst->Instruction.NumSrcRegs) {
340 for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
351 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
399 /* No declarations allowed after the first instruction.
402 report_error( ctx, "Instruction expected but declaration found" )
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_pstipple.c | 248 * TGSI instruction transform callback.
249 * Before the first instruction, insert our new code to sample the
268 /* emit our new declarations before the first instruction */
358 newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
359 newInst.Instruction.NumDstRegs = 1;
362 newInst.Instruction.NumSrcRegs = 2;
371 newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
372 newInst.Instruction.NumDstRegs = 1;
375 newInst.Instruction.NumSrcRegs = 2;
376 newInst.Instruction.Texture = TRUE
[all...] |
| /external/v8/src/ |
| lithium-allocator.h | 63 // For each lithium instruction there are exactly two lifetime positions:
64 // the beginning and the end of the instruction. Lifetime positions for
69 // the instruction with the given index.
79 // Returns the index of the instruction to which this lifetime position
86 // Returns true if this lifetime position corresponds to the instruction
92 // Returns the lifetime position for the start of the instruction which
99 // Returns the lifetime position for the end of the instruction which
106 // Returns the lifetime position for the beginning of the next instruction.
113 // instruction.
121 // instruction
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | 190 static Instruction *getInsertPointForUses(Instruction *User, Value *Def,
196 Instruction *InsertPt = 0;
210 assert((!isa<Instruction>(Def) ||
211 DT->dominates(cast<Instruction>(Def), InsertPt)) &&
257 if (Incr == 0 || Incr->getOpcode() != Instruction::FAdd) return;
270 Instruction *U1 = cast<Instruction>(*IncrUse++);
272 Instruction *U2 = cast<Instruction>(*IncrUse++)
[all...] |
| /cts/tools/dasm/src/dasm/ |
| DAsm.java | 144 * method is called, it checks if there was a jump to current instruction
532 throwDasmError("Missing arguments for instruction " + name);
551 throwDasmError("Bad arguments for instruction " + name + "("
573 throwDasmError("Bad arguments for instruction " + name + "(" + val
589 throwDasmError("Bad arguments for instruction " + name + "("
606 throwDasmError("Bad arguments for instruction " + name + "(" + val
629 throwDasmError("Bad arguments for instruction " + name + "("
636 throwDasmError("Bad arguments for instruction " + name + "("
653 throwDasmError("Bad arguments for instruction " + name + "("
676 throwDasmError("Bad arguments for instruction " + name + "(
[all...] |
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 29 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
86 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
94 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
99 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
101 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
103 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
|
| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
95 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
100 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
102 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
104 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
106 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| LocalVariableInfo.java | 173 * Adds an assignment association for the given instruction and
174 * register spec. This throws an exception if the instruction
177 * <b>Note:</b> Although the instruction contains its own spec for
180 * simple type and the one in the instruction can be an arbitrary
183 * @param insn {@code non-null;} the instruction in question
201 * Gets the named register being assigned by the given instruction, if
204 * @param insn {@code non-null;} instruction in question
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| LocalVariableInfo.java | 176 * Adds an assignment association for the given instruction and
177 * register spec. This throws an exception if the instruction
180 * <b>Note:</b> Although the instruction contains its own spec for
183 * simple type and the one in the instruction can be an arbitrary
186 * @param insn {@code non-null;} the instruction in question
204 * Gets the named register being assigned by the given instruction, if
207 * @param insn {@code non-null;} instruction in question
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| LocalVariableInfo.java | 173 * Adds an assignment association for the given instruction and
174 * register spec. This throws an exception if the instruction
177 * <b>Note:</b> Although the instruction contains its own spec for
180 * simple type and the one in the instruction can be an arbitrary
183 * @param insn {@code non-null;} the instruction in question
201 * Gets the named register being assigned by the given instruction, if
204 * @param insn {@code non-null;} instruction in question
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/windows/ |
| mini_disassembler.h | 67 // can figure out where the next instruction starts, and whether it
76 // Instruction Set Reference for information about operand decoding
93 // Attempts to disassemble a single instruction starting from the
98 // the length in bytes of the instruction.
142 // The instruction type we have decoded from the opcode.
146 // the current instruction (note: we don't care about how large
150 // True iff there is a ModR/M byte in this instruction.
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/windows/ |
| mini_disassembler.h | 67 // can figure out where the next instruction starts, and whether it
76 // Instruction Set Reference for information about operand decoding
93 // Attempts to disassemble a single instruction starting from the
98 // the length in bytes of the instruction.
142 // The instruction type we have decoded from the opcode.
146 // the current instruction (note: we don't care about how large
150 // True iff there is a ModR/M byte in this instruction.
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| LocalVariableInfo.java | 177 * Adds an assignment association for the given instruction and
178 * register spec. This throws an exception if the instruction
181 * <b>Note:</b> Although the instruction contains its own spec for
184 * simple type and the one in the instruction can be an arbitrary
187 * @param insn {@code non-null;} the instruction in question
205 * Gets the named register being assigned by the given instruction, if
208 * @param insn {@code non-null;} instruction in question
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| LocalVariableInfo.java | 174 * Adds an assignment association for the given instruction and
175 * register spec. This throws an exception if the instruction
178 * <b>Note:</b> Although the instruction contains its own spec for
181 * simple type and the one in the instruction can be an arbitrary
184 * @param insn {@code non-null;} the instruction in question
202 * Gets the named register being assigned by the given instruction, if
205 * @param insn {@code non-null;} instruction in question
|
| /external/llvm/include/llvm/MC/ |
| MCAtom.h | 46 /// When modifying a TextAtom, keep instruction boundaries in mind.
47 /// For instance, split must me given the start address of an instruction.
107 /// \brief An entry in an MCTextAtom: a disassembled instruction.
126 /// \brief The address of the next appended instruction, i.e., the
127 /// address immediately after the last instruction in the atom.
130 /// Append an instruction, expanding the atom if necessary.
133 /// \name Instruction list access
|
| /external/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 76 // This def has a non-debug use. Don't delete the instruction!
82 // If there are no defs with uses, the instruction is dead.
117 // If the instruction is dead, delete it!
121 // instruction. Examine each def operand for such references;
146 // MII is now pointing to the next instruction to process,
170 // both defined and used in the same instruction.
182 // We didn't delete the current instruction, so increment MII to
|
| ExpandPostRAPseudos.cpp | 1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
60 "Post-RA pseudo instruction expansion pass", false, false)
62 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
64 /// operands from MI to the replacement instruction.
107 // No need to insert an identify copy instruction.
149 // No need to insert an identity copy instruction, but replace with a KILL
153 // instruction with KILL.
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInst.cpp | 62 // Return whether the instruction is a legal new-value producer.
79 // Return whether the instruction needs to be constant extended.
80 // 1) Always return true if the instruction has 'isExtended' flag set.
99 // We could be using an instruction with an extendable immediate and shoehorn
108 // If the extendable operand is not 'Immediate' type, the instruction should
116 // Return whether the instruction must be always extended.
122 // Return true if the instruction may be extended based on the operand value.
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to LMUL instruction
60 // Corresponds to MACCU instruction
63 // Corresponds to MACCS instruction
66 // Corresponds to CRC8 instruction
|
| /external/oprofile/events/ppc/e300/ |
| events | 5 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
14 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
17 event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)
18 event:0x3e counters:0,1,2,3 um:zero minimum:500 name:MMU_MISSES : Counts instruction TLB miss exceptions
38 event:0x6a counters:0,1,2,3 um:zero minimum:500 name:STALLED_FLOAT : Cycles that completion is stalled due to fp instruction
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionExpander.cpp | 32 Instruction::CastOps Op,
45 Instruction *Ret = NULL;
77 // instruction with different dominance properties than a cast
89 Instruction::CastOps Op = CastInst::getCastOpcode(V, false, Ty, false);
90 assert((Op == Instruction::BitCast ||
91 Op == Instruction::PtrToInt ||
92 Op == Instruction::IntToPtr) &&
98 if (Op == Instruction::BitCast) {
107 if ((Op == Instruction::PtrToInt || Op == Instruction::IntToPtr) &
[all...] |
| /external/llvm/lib/IR/ |
| Verifier.cpp | 35 // * It is illegal to have a ret instruction that returns a value that does not
38 // * A landing pad is defined by a landingpad instruction, and can be jumped to
39 // only by the unwind edge of an invoke instruction.
40 // * A landingpad instruction must be the first non-PHI instruction in the
139 /// dominance checks for the case when an instruction has an operand that is
140 /// an instruction in the same block.
141 SmallPtrSet<Instruction*, 16> InstsInThisBlock;
268 void visit(Instruction &I);
295 void verifyDominatesUse(Instruction &I, unsigned i)
[all...] |
