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/external/dexmaker/src/dx/java/com/android/dx/rop/code/
BasicBlockList.java	102 * Gets the total instruction count for this instance. This is the 103 * sum of the instruction counts of each block. 105 * @return {@code >= 0;} the total instruction count 122 * Gets the total instruction count for this instance, ignoring 125 * @return {@code >= 0;} the total instruction count 169 * Visits each instruction of each block in the list, in order. 185 * the registers in each instruction are offset by the given 310 * Instruction visitor class for counting registers used. 366 * @param insn {@code non-null;} instruction being visited
/external/llvm/include/llvm/CodeGen/
SelectionDAGISel.h	11 // base class for SelectionDAG-based instruction selectors. 41 /// pattern-matching instruction selectors. 72 /// instruction selection starts. 85 /// (which will appear in the machine instruction) should be added to the 94 /// operand node N of U during instruction selection that starts at Root. 98 /// U can be folded during instruction selection that starts at Root. 173 /// DAGSize - Size of DAG being instruction selected. 253 /// \brief Perform instruction selection on all basic blocks in the function. 256 /// \brief Perform instruction selection on a single basic block, for
/external/llvm/include/llvm/MC/
MCSchedule.h	11 // for scheduling and other instruction cost heuristics. 39 // instruction interlocking that may stall the pipeline). 61 /// an instruction with invalid latency to have infinite latency. Also identify 73 /// Specify the number of cycles allowed after instruction issue before a 92 /// Summarize the scheduling resources required for an instruction of a 127 /// instruction type. Itinerary tables are an independant mechanism that 128 /// provides a detailed reservation table describing each cycle of instruction 183 // Instruction itinerary tables used by InstrItineraryData. 216 /// Does this machine model include instruction-level scheduling.
/external/llvm/lib/CodeGen/
MachineInstrBundle.cpp	36 "Unpack machine instruction bundles", false, false) 47 // Remove BUNDLE instruction and the InsideBundle flags from bundled 87 "Finalize machine instruction bundles", false, false) 94 /// finalizeBundle - Finalize a machine instruction bundle which includes 96 /// This routine adds a BUNDLE instruction to represent the bundle, it adds 99 /// instruction. 206 /// the last instruction in the bundle is not provided as an input. This is 208 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that 221 /// finalizeBundles - Finalize instruction bundles in the specified
/external/llvm/lib/Target/Mips/
MipsInstrInfo.cpp	1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===// 46 /// instruction. 170 /// specified Branch instruction. 207 // Get the second to last instruction in the block. 220 // If there is only one terminator instruction, process it. 240 // If second to last instruction is an unconditional branch, 241 // analyze it and remove the last instruction. 243 // Return if the last instruction cannot be removed. 264 /// Return the number of bytes of code the specified instruction may be.
Mips16InstrInfo.h	1 //===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===// 30 /// isLoadFromStackSlot - If the specified machine instruction is a direct 33 /// not, return 0. This predicate must return 0 if the instruction has 38 /// isStoreToStackSlot - If the specified machine instruction is a direct 41 /// not, return 0. This predicate must return 0 if the instruction has
MipsInstrInfo.h	1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===// 70 /// Insert nop instruction when hazard condition is found 75 /// such, whenever a client has an instance of instruction info, it should 82 /// Return the number of bytes of code the specified instruction may be. 115 /// Create an instruction which has the same operands and memory operands
MipsOptimizeMathLibCalls.cpp	129 // instruction if the call has already been marked read-only. 139 // v0 = sqrt_noreadmem(src) # native sqrt instruction. 156 Instruction *LibCall = Call->clone(); 160 // Add attribute "readnone" so that backend can use a native sqrt instruction 161 // for this call. Insert a FP compare instruction and a conditional branch
/external/llvm/lib/Transforms/IPO/
IPConstantPropagation.cpp	94 // Used by a non-instruction, or not the callee of a function, do not 99 CallSite CS(cast<Instruction>(U)); 225 Instruction* Call = CS.getInstruction(); 227 // Not a call instruction or a call instruction that's not calling F 242 // the call instruction and use that. 250 Instruction *Ins = cast<Instruction>(*I); 268 // the call instruction and use that.
/external/llvm/lib/Transforms/ObjCARC/
DependencyAnalysis.cpp	32 /// Test whether the given instruction can result in a reference count 35 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, 69 /// Test whether the given instruction can "use" the given pointer's object in a 72 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, 117 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, 207 BasicBlock *StartBB, Instruction *StartInst, 208 SmallPtrSet<Instruction *, 4> &DependingInsts, 237 Instruction *Inst = --LocalStartPos; 257 DependingInsts.insert(reinterpret_cast<Instruction *>(-1));
/external/llvm/lib/Transforms/Scalar/
SCCP.cpp	70 /// overdefined - This instruction is not known to be constant, and we know 303 // is not already a constant, add it to the instruction work list so that 304 // the users of the instruction are updated later. 333 // value is not already overdefined, add it to the overdefined instruction 334 // work list so that the users of the instruction are updated later. 440 // successors are reachable from a given terminator instruction. 450 // instruction that was just changed state somehow. Based on this 451 // information, we need to update the specified user of this instruction. 453 void OperandChangedState(Instruction *I) { 461 // visit implementations - Something changed in this instruction. Either a     [all...]
LoopInstSimplify.cpp	1 //===- LoopInstSimplify.cpp - Loop Instruction Simplification Pass --------===// 10 // This pass performs lightweight instruction simplification on loop bodies. 77 SmallPtrSet<const Instruction*, 8> S1, S2, *ToSimplify = &S1, *Next = &S2; 102 Instruction *I = BI++; 117 Next->insert(cast<Instruction>(*UI));
/external/mesa3d/src/mesa/drivers/dri/i965/
brw_wm_pass0.c	56 /** return pointer to a newly allocated instruction */ 60 memset(&c->instruction[c->nr_insns], 0, sizeof(*c->instruction)); 61 return &c->instruction[c->nr_insns++]; 241 * Straight translation to internal instruction format 295 newref->insn = insn - c->instruction; 321 /* Copy some data out of the instruction 406 * an instruction produces duplicate values (eg DP3), all are given 424 /* Optimize away moves, otherwise emit translated instruction:
/external/v8/src/arm/
assembler-arm-inl.h	335 // If we have a bx instruction, the instruction before the bx is 345 // If we have a blx instruction, the instruction before it is 356 // Verify that the constant pool comes after the instruction referencing it. 381 // Intuitively, we would think it is necessary to flush the instruction cache 384 // However, on ARM, no instruction was actually patched by the assignment 385 // above; the target address is not part of an instruction, it is patched in 386 // the constant pool and is read via a data access; the instruction accessing
/external/llvm/docs/
LangRef.rst	51 instruction is syntactically okay, but not well formed: 134 demonstrating instructions, we will follow an instruction with a comment 570 :ref:`terminator <terminators>` instruction (such as a branch or function     [all...]
/external/qemu/
ppc-dis.c	142 /* Opcode is an e500 SPE floating point instruction. */ 169 /* A macro to extract the major opcode from an instruction. */ 180 /* How far the operand is left shifted in the instruction. 186 operand value into an instruction, check this field. 190 (i is the instruction which we are filling in, o is a pointer to 194 instruction and the operand value. It will return the new value 195 of the instruction. If the ERRMSG argument is not NULL, then if 201 (unsigned long instruction, long op, int dialect, const char **errmsg); 204 extract this operand type from an instruction, check this field. 210 (i is the instruction, o is a pointer to this structure, and o     [all...]
/dalvik/dx/src/com/android/dx/ssa/
DeadCodeRemover.java	139 // Delete this instruction completely if it has sources 144 // Delete this instruction from all usage lists. 150 // Remove this instruction result from the sources of any phis 209 * @param insn {@code null-ok;} instruction in question 225 * registers defined by an instruction with no side effect.
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_code.h	190 int tex_offset; /**< first tex instruction */ 191 int tex_end; /**< last tex instruction, relative to tex_offset */ 192 int alu_offset; /**< first ALU instruction */ 193 int alu_end; /**< last ALU instruction, relative to alu_offset */ 238 int inst_end; /* Number of instructions - 1; also, last instruction to be executed */
/external/llvm/docs/CommandGuide/
tblgen.rst	77 Generate instruction descriptions. 89 Generate pseudo instruction lowering. 93 Generate a DAG (Directed Acycle Graph) instruction selector. 97 Generate assembly instruction matcher. 105 Generate a "fast" instruction selector.
/external/llvm/lib/IR/
IntrinsicInst.cpp	1 //===-- InstrinsicInst.cpp - Intrinsic Instruction Wrappers -----*- C++ -*-===// 13 // All intrinsic function calls are instances of the call instruction, so these 20 // cast instruction needs to be stripped away. 53 /// DbgDeclareInst - This represents the llvm.dbg.declare instruction. 64 /// DbgValueInst - This represents the llvm.dbg.value instruction.
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonBaseInfo.h	26 /// instruction info tracks. 73 NoMemAccess = 0, // Not a memory acces instruction. 74 ByteAccess = 1, // Byte access instruction (memb). 75 HalfWordAccess = 2, // Half word access instruction (memh). 77 DoubleWordAccess = 4 // Double word access instruction (memd)
/external/llvm/lib/Target/X86/Disassembler/
X86DisassemblerDecoderCommon.h	46 * Attributes of an instruction that must be known before the opcode can be 69 * Combinations of the above attributes that are relevant to instruction 71 * these without affecting the ultimately decoded instruction. 76 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ 77 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ 242 * determining the instruction's class (i.e., which IC_* constant applies to 257 * instruction is the same. 259 * corresponds to one instruction; otherwise, it corresponds to 260 * a different instruction. 262 * divided by 8 is used to select instruction; otherwise, eac     [all...]
/external/llvm/utils/TableGen/
TableGen.cpp	57 "Generate instruction descriptions"), 65 "Generate pseudo instruction lowering"), 67 "Generate assembly instruction matcher"), 69 "Generate a DAG instruction selector"), 73 "Generate a \"fast\" instruction selector"),
/external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_code.h	190 int tex_offset; /**< first tex instruction */ 191 int tex_end; /**< last tex instruction, relative to tex_offset */ 192 int alu_offset; /**< first ALU instruction */ 193 int alu_end; /**< last ALU instruction, relative to alu_offset */ 238 int inst_end; /* Number of instructions - 1; also, last instruction to be executed */
/external/oprofile/events/mips/74K/
events	22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses 24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions 25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles 26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles 27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer 38 event:0x14 counters:0,2 um:zero minimum:500 name:SINGLE_ISSUE_CYCLES : 20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles 39 event:0x15 counters:0,2 um:zero minimum:500 name:OOO_ALU_ISSUE_CYCLES : 21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool) 43 event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses 52 event:0x23 counters:0,2 um:zero minimum:500 name:LOAD_MISS_CONSUMER_REPLAYS : 35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduate     [all...]

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