| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| strcmp.S | 483 ldrh w2, [wp2]
|
| /dalvik/vm/compiler/codegen/mips/ |
| Assemble.cpp | [all...] |
| /external/chromium_org/third_party/skia/src/opts/ |
| SkBlitRow_opts_arm.cpp | 53 "ldrh r4, [%[dst]] \n\t"
|
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| filter_v6.asm | 340 ldrh r9, [r0, #12]
|
| /external/pixman/pixman/ |
| pixman-arm-simd-asm.S | 123 ldrh SRC, [sp, #ARGS_STACK_OFFSET]
|
| /external/skia/src/opts/ |
| SkBlitRow_opts_arm.cpp | 53 "ldrh r4, [%[dst]] \n\t"
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_BitDec_s.h | 518 LDRH $Symbol, [$pVLDTable, $Symbol] ;// load table entry
|
| armCOMM_s.h | 534 _M_DATA "LDRH",2,$r,$a0,$a1,$a2,$a3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_BitDec_s.h | 518 LDRH $Symbol, [$pVLDTable, $Symbol] ;// load table entry
|
| armCOMM_s.h | 537 _M_DATA "LDRH",2,$r,$a0,$a1,$a2,$a3
|
| /external/llvm/test/MC/AArch64/ |
| basic-a64-diagnostics.s | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrThumb2.td | [all...] |
| ARMScheduleSwift.td | [all...] |
| ARMBaseRegisterInfo.cpp | 496 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
|
| ARMInstrInfo.td | [all...] |
| README.txt | 128 ldrh r1, [r1, #+4]
|
| ARMBaseInstrInfo.cpp | [all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.cc | 483 void ArmAssembler::ldrh(Register rd, Address ad, Condition cond) { function in class:art::arm::ArmAssembler
[all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-armv5te-vfp.S | 113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
134 ldrh _dreg, [_sreg, #((_count)*2)]!
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
[all...] |
| InterpAsm-armv7-a-neon.S | 113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
134 ldrh _dreg, [_sreg, #((_count)*2)]!
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
[all...] |
| InterpAsm-armv7-a.S | 113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
134 ldrh _dreg, [_sreg, #((_count)*2)]!
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
[all...] |
| InterpAsm-armv5te.S | 113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
134 ldrh _dreg, [_sreg, #((_count)*2)]!
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.c | 263 * ldrh/strh offset: between -0xff and 0xff
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 925 void ldrh(Register dst, const MemOperand& src, Condition cond = al);
[all...] |
