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  /external/llvm/lib/Target/ARM/
ARMISelLowering.h 180 // is fine if BUILD_VECTORs are always lowered to shuffles or other
ARMTargetTransformInfo.cpp 400 // On NEON a a vector select gets lowered to vbsl.
  /external/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 204 // TRAP can be lowered to PTX trap
    [all...]
NVPTXAsmPrinter.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.h 90 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
  /external/llvm/lib/Target/X86/
X86InstrCompiler.td 110 // When using segmented stacks these are lowered into instructions which first
202 // This is lowered into a RET instruction by MCInstLower. We need
209 // This instruction is lowered to a RET followed by a MOV. The two
    [all...]
  /external/llvm/test/CodeGen/SystemZ/
frame-14.ll 200 ; The LA then gets lowered into the LLILH/LA form. The exact sequence
frame-16.ll 190 ; The LA then gets lowered into the LLILH/LA form. The exact sequence
  /external/llvm/test/Instrumentation/MemorySanitizer/
msan_basic.ll 238 ; memmove is lowered to a call
  /external/mesa3d/docs/
relnotes-7.11.1.html 221 <li>ir_to_mesa: Emit warnings instead of errors for IR that can't be lowered</li>
  /external/mesa3d/src/gallium/drivers/nv50/codegen/
nv50_ir.h 159 TYPE_U64, // 64 bit operations are only lowered after register allocation
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_fs_emit.cpp 316 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
brw_vec4_emit.cpp 385 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
  /external/oprofile/events/i386/nehalem/
events 8 # lowered in many cases without ill effect.
  /external/qemu/hw/
mc146818rtc.c 91 * be lowered in any case
  /external/smack/src/org/xbill/DNS/
Cache.java 145 * the maximum size is lowered, but it should shrink as
  /frameworks/base/media/tests/MediaFrameworkTest/src/com/android/mediaframeworktest/functional/audio/
MediaVisualizerTest.java 485 // check capture on sound with music volume lowered from max
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp 422 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
447 /// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
448 /// the corresponding (lowered) CALLSEQ_BEGIN node.
480 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
545 // If we're scheduling a lowered CALLSEQ_END, find the corresponding
    [all...]
LegalizeVectorOps.cpp 23 // or operations that happen to take a vector which are custom-lowered;
SelectionDAGISel.cpp 530 // Final step, emit the lowered DAG as machine code.
603 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 347 /// being lowered. Returns a SDNode with the same number of values as the
    [all...]
  /external/clang/www/
cxx_status.html 395 <span id="n2664">(3): <code>memory_order_consume</code> is lowered to
  /external/llvm/lib/CodeGen/AsmPrinter/
DwarfException.cpp 369 // by try-range labels when lowered). Ordinary calls do not, so appropriate
  /external/llvm/lib/CodeGen/
Passes.cpp 562 // there is one known exception: lowered code for arguments that are only
StrongPHIElimination.cpp 192 STATISTIC(NumPHIsLowered, "Number of PHIs lowered");

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