| /external/llvm/test/CodeGen/ARM/ |
| vbsl.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
112 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
119 %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
126 %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
133 %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
140 %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
147 %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
154 %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
161 %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
168 %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwin
[all...] |
| vsra.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
168 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
178 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
188 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
198 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
208 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
218 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
228 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
238 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
248 %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 (…)
[all...] |
| fmacs.ll | 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
12 ; NEON-LABEL: t1:
13 ; NEON: vmla.f32
28 ; NEON-LABEL: t2:
29 ; NEON: vmla.f64
44 ; NEON-LABEL: t3:
45 ; NEON: vmla.f32
|
| select.ll | 3 ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
78 ; CHECK-NEON: _f8:
79 ; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
80 ; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
81 ; CHECK-NEON-NEXT: cmp r0, [[R3]]
82 ; CHECK-NEON-NEXT: it eq
83 ; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4
84 ; CHECK-NEON-NEXT: ldr
85 ; CHECK-NEON: b
[all...] |
| vldlane.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
2 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
103 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
116 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
128 %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
142 %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
156 %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
169 %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
182 %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
194 %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1
[all...] |
| /ndk/sources/android/cpufeatures/ |
| cpu-features.h | 70 * instead of 16. Note that ARM mandates this feature is the 'NEON'
73 * NEON:
75 * NEON. Note that this mandates the VFP_D32 feature as well, per the
89 * Fused multiply-accumulate NEON instructions extension. Optional
130 * -mfpu=neon
132 * also support NEON intrinsics (see <arm_neon.h>).
133 * Generated code requires VFPv3|VFP_D32|NEON features.
141 * -mfpu=neon-vfpv4
142 * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|NEON|NEON_FMA
148 * NEON|NEON_FMA|IDIV_ARM|IDIV_THUMB
[all...] |
| /frameworks/rs/driver/runtime/arch/ |
| neon.ll | 8 declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
9 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
10 declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
11 declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
12 declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
13 declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
14 declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
15 declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
17 declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
18 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnon
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| complex-copy-noneon.ll | 1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-neon < %s
4 ; previously. This probably shouldn't happen without NEON, but the most
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
| ivchain-ARM.ll | 241 %12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %.05, i32 1) nounwind
243 %14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %13, i32 1) nounwind
249 %19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %18, i32 1) nounwind
251 %21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %20, i32 1) nounwind
257 %26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %25, i32 1) nounwind
259 %28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %27, i32 1) nounwind
265 %33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %32, i32 1) nounwind
267 %35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %34, i32 1) nounwind
292 declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*, i32) nounwind readonly
330 %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr, i32 1
[all...] |
| /external/oprofile/events/arm/armv7/ |
| events | 17 event:0x4C counters:1,2,3,4 um:zero minimum:500 name:L1_NEON_DATA : NEON data access that hits L1 cache
18 event:0x4D counters:1,2,3,4 um:zero minimum:500 name:L1_NEON_CACH_DATA : NEON cacheable data access that hits L1 cache
19 event:0x4E counters:1,2,3,4 um:zero minimum:500 name:L2_NEON : L2 access as a result of NEON memory access
20 event:0x4F counters:1,2,3,4 um:zero minimum:500 name:L2_NEON_HIT : Any NEON hit in L2 cache
29 event:0x58 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_NEON_DATA_STALL : Number of cycles the processor waits on MRC data from NEON
30 event:0x59 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_NEON_INST_STALL : Number of cycles the processor waits on NEON instruction queue or NEON load queue
31 event:0x5A counters:1,2,3,4 um:zero minimum:500 name:NEON_CYCLES : Number of cycles NEON and integer processors are not idle
|
| /ndk/tests/build/build-mode/jni/ |
| main.c | 42 # error "This source file should be compiled with NEON support!"
46 # error "This source file should be compiled without NEON support!"
|
| /build/target/board/generic/ |
| BoardConfig.mk | 11 # Note: we build the platform images for ARMv7-A _without_ NEON.
13 # Technically, the emulator supports ARMv7-A _and_ NEON instructions, but
14 # emulated NEON code paths typically ends up 2x slower than the normal C code
18 # What this means is that the platform image will not use NEON code paths
20 # application code generated with the NDK that uses NEON in the emulator.
|
| /frameworks/compile/libbcc/lib/Support/ |
| TargetCompilerConfigs.cpp | 70 if (pEnableNEON && Features.count("neon") && Features["neon"]) {
71 pAttributes.push_back("+neon");
73 pAttributes.push_back("-neon");
92 // Enable NEON by default.
|
| /external/pixman/pixman/ |
| Makefile.am | 69 # arm neon code
71 noinst_LTLIBRARIES += libpixman-arm-neon.la
73 pixman-arm-neon.c \
75 pixman-arm-neon-asm.S \
76 pixman-arm-neon-asm-bilinear.S \
77 pixman-arm-neon-asm.h
78 libpixman_1_la_LIBADD += libpixman-arm-neon.la
|
| /bionic/libc/arch-arm/krait/bionic/ |
| memcpy.S | 29 /* Assumes neon instructions and a cache line size of 32 bytes. */
36 * instructions, that supports neon instructions, and that has a 32 byte
42 .fpu neon
|
| /external/valgrind/main/none/tests/arm/ |
| Makefile.am | 45 -mfpu=neon \
50 -mfpu=neon \
54 -mfpu=neon \
|
| /external/webrtc/src/modules/audio_processing/aecm/ |
| Android.mk | 10 # Build the non-neon library.
58 # Build the neon library.
73 -mfpu=neon \
|
| /external/webrtc/src/modules/audio_processing/ns/ |
| Android.mk | 10 # Build the non-neon library.
60 # Build the neon library.
75 -mfpu=neon \
|
| /dalvik/vm/compiler/codegen/arm/armv7-a-neon/ |
| ArchVariant.h | 23 #include "../../../template/armv7-a-neon/TemplateOpList.h"
|
| /dalvik/vm/compiler/template/ |
| rebuild.sh | 22 for arch in ia32 armv5te armv5te-vfp armv7-a armv7-a-neon mips; do TARGET_ARCH_EXT=$arch make -f Makefile-template; done
|
| /development/ndk/samples/hello-neon/ |
| build.properties | 20 application.package=com.example.neon
|
| /device/generic/mips/ |
| mini_mips.mk | 15 $(call inherit-product, device/generic/armv7-a-neon/mini_common.mk)
|
| /device/generic/x86/ |
| mini_x86.mk | 15 $(call inherit-product, device/generic/armv7-a-neon/mini_common.mk)
|
| /external/chromium_org/third_party/skia/src/opts/ |
| SkXfermode_opts_arm_neon.h | 24 // it with -mfpu=neon.
|
| /external/libvpx/armv7a/ |
| vpx_config.c | 8 static const char* const cfg = "--target=armv7-android-gcc --disable-runtime-cpu-detect --sdk-path=/usr/local/google/home/hkuang/Downloads/android-ndk-r8e --disable-vp9-encoder --disable-neon --disable-examples --disable-docs --enable-realtime-only";
|
