| /external/chromium_org/third_party/re2/re2/ |
| bitstate.cc | 125 int op = prog_->inst(id)->opcode();
171 switch (ip->opcode()) {
174 LOG(DFATAL) << "Unexpected opcode: " << ip->opcode() << " arg " << arg;
201 // One opcode is byte range; the other leads to match.
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 188 llvm_unreachable("Unexpected Opcode");
209 llvm_unreachable("Unexpected Opcode");
237 llvm_unreachable("Unexpected Opcode");
252 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
254 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode();
81 if (Opcode == XCore::STWFI)
129 /// the correspondent Branch instruction opcode.
142 /// opcode that matches the cc.
389 /// ReverseBranchCondition - Return the inverse opcode of the
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_emit.c | 184 * \param opcode the instruction opcode
191 uint opcode,
239 i915_emit_texld( p, tmp, A0_DEST_CHANNEL_ALL, sampler, coord, opcode, num_coord );
260 *(p->csr++) = (opcode |
|
| i915_fpc_translate.c | 415 uint opcode,
429 opcode,
436 * \param opcode the i915 opcode
442 uint opcode, uint numArgs,
454 opcode,
467 uint opcode, uint numArgs,
479 emit_simple_arith(p, &inst2, opcode, numArgs, fs);
501 switch (inst->Instruction.Opcode) {
675 T0_TEXKILL, /* opcode */
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_visitor.cpp | 34 enum opcode opcode, dst_reg dst,
37 this->opcode = opcode;
66 vec4_visitor::emit(enum opcode opcode, dst_reg dst,
69 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst,
75 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1)
77 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0, src1))
[all...] |
| brw_optimize.c | 92 return brw_opcodes[inst->header.opcode].is_arith;
120 if (brw_opcodes[inst->header.opcode].ndst == 0)
139 if (inst->header.opcode == BRW_OPCODE_SEND) {
163 if (brw_opcodes[inst->header.opcode].ndst == 0)
242 if (inst->header.opcode != BRW_OPCODE_SEND ||
261 if (inst->header.opcode != BRW_OPCODE_SEND)
297 if (brw_opcodes[inst->header.opcode].nsrc == 0)
305 if (brw_opcodes[inst->header.opcode].nsrc >= 1) {
340 if (brw_opcodes[inst->header.opcode].nsrc >= 2) {
431 if ((!brw_is_predicated(inst) || inst->header.opcode == BRW_OPCODE_SEL) &
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.h | 340 gl_inst_opcode Opcode;
439 _mesa_num_inst_src_regs(gl_inst_opcode opcode);
442 _mesa_num_inst_dst_regs(gl_inst_opcode opcode);
445 _mesa_is_tex_instruction(gl_inst_opcode opcode);
451 _mesa_opcode_string(gl_inst_opcode opcode);
|
| /external/openssl/crypto/sha/asm/ |
| sha512-parisc.pl | 698 { my $opcode=(0x14<<26)|($2<<21)|($3<<16)|(($1&0x1FF8)<<1)|(($1>>13)&1);
699 $opcode|=(1<<3) if ($mod =~ /^,m/);
700 $opcode|=(1<<2) if ($mod =~ /^,mb/);
701 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
711 { my $opcode=(0x1c<<26)|($3<<21)|($1<<16)|(($2&0x1FF8)<<1)|(($2>>13)&1);
712 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
723 { my $opcode=(0x36<<26)|($1<<21)|($4<<16);
725 $opcode |= (($2&0x20)<<6)|(($2&0x1f)<<5); # encode pos
726 $opcode |= (($len&0x20)<<7)|($len&0x1f); # encode len
727 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig
[all...] |
| /external/regex-re2/re2/ |
| bitstate.cc | 125 int op = prog_->inst(id)->opcode();
171 switch (ip->opcode()) {
174 LOG(DFATAL) << "Unexpected opcode: " << ip->opcode() << " arg " << arg;
201 // One opcode is byte range; the other leads to match.
|
| /external/chromium_org/third_party/sqlite/src/src/ |
| vdbeaux.c | 130 ** op The opcode for this instruction
152 pOp->opcode = (u8)op;
161 /* Any program that uses the OP_ParseSchema opcode needs to lock
188 ** Add an opcode that includes the p4 value as a pointer.
191 Vdbe *p, /* Add the opcode to this VM */
192 int op, /* The new opcode */
205 ** Add an opcode that includes the p4 value as an integer.
208 Vdbe *p, /* Add the opcode to this VM */
209 int op, /* The new opcode */
369 int opcode = pOp->opcode local
412 u8 opcode = pOp->opcode; local
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 124 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
128 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
142 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
143 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
165 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
166 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
185 /// FactorizeBinOp - Simplify "LHS Opcode RHS" by factorizing out a common term
186 /// using the operation OpCodeToExtract. For example, when Opcode is Add and
189 static Value *FactorizeBinOp(unsigned Opcode, Value *LHS, Value *RHS,
215 if (Value *V = SimplifyBinOp(Opcode, B, DD, Q, MaxRecurse))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_compiler_util.c | 132 switch (info->Opcode) {
193 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
227 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
423 rc_get_opcode_info(inst->U.I.Opcode);
440 if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE) {
560 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
612 * @return The opcode of inst if it is a flow control instruction.
618 info = rc_get_opcode_info(inst->U.I.Opcode);
620 info = rc_get_opcode_info(inst->U.P.RGB.Opcode);
624 inst->U.P.Alpha.Opcode == RC_OPCODE_NOP)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_optimize.c | 92 return brw_opcodes[inst->header.opcode].is_arith;
120 if (brw_opcodes[inst->header.opcode].ndst == 0)
139 if (inst->header.opcode == BRW_OPCODE_SEND) {
163 if (brw_opcodes[inst->header.opcode].ndst == 0)
242 if (inst->header.opcode != BRW_OPCODE_SEND ||
261 if (inst->header.opcode != BRW_OPCODE_SEND)
297 if (brw_opcodes[inst->header.opcode].nsrc == 0)
305 if (brw_opcodes[inst->header.opcode].nsrc >= 1) {
340 if (brw_opcodes[inst->header.opcode].nsrc >= 2) {
431 if ((!brw_is_predicated(inst) || inst->header.opcode == BRW_OPCODE_SEL) &
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler_util.c | 132 switch (info->Opcode) {
193 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
227 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
423 rc_get_opcode_info(inst->U.I.Opcode);
440 if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE) {
560 const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
612 * @return The opcode of inst if it is a flow control instruction.
618 info = rc_get_opcode_info(inst->U.I.Opcode);
620 info = rc_get_opcode_info(inst->U.P.RGB.Opcode);
624 inst->U.P.Alpha.Opcode == RC_OPCODE_NOP)
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/file/ |
| DebugInfoDecoder.java | 284 int opcode = bs.read(); local
286 if (opcode < 0) {
292 switch (opcode) {
395 if (opcode < DBG_FIRST_SPECIAL) {
397 "Invalid extended opcode encountered "
398 + opcode);
401 int adjopcode = opcode - DBG_FIRST_SPECIAL;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/main/ |
| dlist.c | 105 struct gl_list_instruction Opcode[MAX_DLIST_EXT_OPCODES];
493 } OpCode;
510 OpCode opcode; member in union:gl_dlist_node
522 void *next; /* If prev node's opcode==OPCODE_CONTINUE */
577 dlist->Head[0].opcode = OPCODE_END_OF_LIST;
593 /** Is the given opcode an extension code? */
595 is_ext_opcode(OpCode opcode)
597 return (opcode >= OPCODE_EXT_0)
651 const OpCode opcode = n[0].opcode; local
7692 const OpCode opcode = n[0].opcode; local
10703 const OpCode opcode = n[0].opcode; local
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 757 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
758 const uint64_t F = get(Opcode).TSFlags;
769 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
807 // This will change MI's opcode to its predicate version.
983 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.cpp | 147 OS.indent(indent) << "CheckOpcode " << Opcode.getEnumName() << '\n';
281 return HashString(Opcode.getEnumName());
310 // to ensure that the nodes are for the same opcode.
311 return cast<CheckOpcodeMatcher>(M)->Opcode.getEnumName() ==
312 Opcode.getEnumName();
366 // to ensure that the nodes are for the same opcode.
374 // If checking for a result the opcode doesn't have, it can't match.
|
| /external/mesa3d/src/mesa/main/ |
| dlist.c | 105 struct gl_list_instruction Opcode[MAX_DLIST_EXT_OPCODES];
493 } OpCode;
510 OpCode opcode; member in union:gl_dlist_node
522 void *next; /* If prev node's opcode==OPCODE_CONTINUE */
577 dlist->Head[0].opcode = OPCODE_END_OF_LIST;
593 /** Is the given opcode an extension code? */
595 is_ext_opcode(OpCode opcode)
597 return (opcode >= OPCODE_EXT_0)
651 const OpCode opcode = n[0].opcode; local
7692 const OpCode opcode = n[0].opcode; local
10703 const OpCode opcode = n[0].opcode; local
[all...] |
| /sdk/emulator/opengl/host/tools/emugen/ |
| README | 28 unsigned int opcode;
46 101, // foo opcode
47 14, // sizeof(opcode) + sizeof(packet_len) + sizeof(int) + sizeof(short)
85 101, // foo opcode
86 xx, sizeof(opcode) + sizeof(datalen) + sizeof(int) + sizeof(unsigned int) + n * sizeof(int);
169 api_opcodes.h - defines the protocol opcodes. The first opcode value
276 set the base opcode value for this api
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
| i915_fpc_translate.c | 415 uint opcode,
429 opcode,
436 * \param opcode the i915 opcode
442 uint opcode, uint numArgs,
454 opcode,
467 uint opcode, uint numArgs,
479 emit_simple_arith(p, &inst2, opcode, numArgs, fs);
501 switch (inst->Instruction.Opcode) {
675 T0_TEXKILL, /* opcode */
[all...] |
| /external/grub/netboot/ |
| main.c | 264 arpreq.opcode = htons (ARP_REQUEST);
320 tp.opcode = htons (TFTP_RRQ);
323 + sizeof (tp.ip) + sizeof (tp.udp) + sizeof (tp.opcode) + 1);
368 if (tr->opcode == ntohs (TFTP_ERROR))
376 if (tr->opcode == ntohs (TFTP_OACK))
407 tp.opcode = htons (TFTP_ERROR);
412 + sizeof (tp.opcode) + sizeof (tp.u.err.errcode)
427 else if (tr->opcode == ntohs (TFTP_DATA))
446 tp.opcode = htons (TFTP_ACK);
497 rarpreq.opcode = htons (RARP_REQUEST)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 237 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
253 Inst.setOpcode(Opcode);
287 unsigned Opcode) {
332 Inst.setOpcode(Opcode);
415 default: llvm_unreachable("Invalid opcode");
439 default: llvm_unreachable("Invalid opcode");
454 unsigned Opcode = OutMI.getOpcode();
457 OutMI.setOpcode(Opcode);
473 unsigned Opcode;
475 default: llvm_unreachable("Invalid opcode");
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| Dops.java | 54 * pseudo-opcode used for nonstandard formatted "instructions"
62 // BEGIN(dops); GENERATED AUTOMATICALLY BY opcode-gen
[all...] |
