| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| RopToDop.java | 49 * The following comment lists each opcode that should be considered
50 * the "head" of an opcode chain, in terms of the process of fitting
51 * an instruction's arguments to an actual opcode. This list is
55 * TODO: Make opcode-gen produce useful code in this case instead
59 // BEGIN(first-opcodes); GENERATED AUTOMATICALLY BY opcode-gen
222 * smallest Dalvik opcode, and leave it to later processing to
450 * Returns the dalvik opcode appropriate for the given register-based
454 * @return the corresponding dalvik opcode; one of the constants in
470 * There was no easy case for the rop, so look up the opcode, and
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| /external/dexmaker/src/dx/java/com/android/dx/dex/file/ |
| DebugInfoEncoder.java | 766 * entry. This will typically be a single special opcode, although
779 int opcode; local
795 opcode = computeOpcode (deltaLines, deltaAddress);
797 if ((opcode & ~0xff) > 0) {
800 opcode = computeOpcode (deltaLines, deltaAddress);
802 if ((opcode & ~0xff) > 0) {
805 opcode = computeOpcode (deltaLines, deltaAddress);
809 output.writeByte(opcode);
821 * Computes a special opcode that will encode the given position change.
|
| /external/javassist/src/main/javassist/bytecode/ |
| ClassFileWriter.java | 43 * mw.add(Opcode.ALOAD_0);
44 * mw.add(Opcode.INVOKESPECIAL);
47 * mw.add(Opcode.RETURN);
52 * mw.add(Opcode.ICONST_1);
53 * mw.add(Opcode.IRETURN);
410 * @see Opcode
433 * @see Opcode
435 public void addInvoke(int opcode, String targetClass, String methodName,
440 add(opcode);
|
| /external/javassist/src/main/javassist/util/proxy/ |
| ProxyFactory.java | [all...] |
| /external/llvm/lib/MC/ |
| MCInst.cpp | 56 // Show the instruction opcode name if we have access to a printer.
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.h | 34 // if there is not such an opcode.
|
| Thumb1InstrInfo.h | 33 // if there is not such an opcode.
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 83 unsigned Opcode = MI.getOpcode();
84 if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
85 Opcode == PPC::BL8_NOP_TLS)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 171 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
172 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
180 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
181 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| /external/llvm/test/CodeGen/X86/ |
| zext-inreg-0.ll | 12 ; This related to not having a ZERO_EXTEND_REG opcode.
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| unpredictable-LSL-regform.txt | 3 # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
|
| unpredictable-RSC-arm.txt | 3 # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
|
| unpredictable-SSAT-arm.txt | 3 # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13)
|
| unpredictable-STRBrs-arm.txt | 3 # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
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| unpredictable-UQADD8-arm.txt | 3 # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4)
|
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 36 /// The opcode of the instruction, as used in an MCInst
42 /// The opcode field from the record; this is the opcode used in the Intel
44 uint8_t Opcode;
|
| /external/mesa3d/src/gallium/auxiliary/rbug/ |
| rbug_internal.h | 39 int rbug_connection_send_start(struct rbug_connection *con, enum rbug_opcode opcode, uint32_t length);
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_scan.h | 64 uint opcode_count[TGSI_OPCODE_LAST]; /**< opcode histogram */
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_rename_regs.c | 59 if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 46 /// LowerROTL - Lower ROTL opcode to BITALIGN
|
| SIISelLowering.h | 54 virtual const char* getTargetNodeName(unsigned Opcode) const;
|
| SIInstrInfo.h | 49 virtual bool isMov(unsigned Opcode) const;
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| radeonsi_pm4.h | 63 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
|
| /external/mesa3d/src/glsl/ |
| lower_texture_projection.cpp | 30 * Many GPUs have a texture sampling opcode that takes the projector
|
| /external/mesa3d/src/mapi/glapi/gen/ |
| glX_doc.py | 132 print ' 2 %-4u rendering command opcode' % (f.glx_rop)
143 print ' 1 CARD8 opcode (X assigned)'
144 print ' 1 %-4u GLX opcode (%s)' % (f.opcode_real_value(), f.opcode_real_name())
156 print ' 4 %-4u vendor specific opcode' % (f.opcode_value())
|
