| /dalvik/vm/mterp/mips/ |
| OP_INVOKE_SUPER.S | 26 bnez a0, .L${opcode}_continue # resolved, continue on
34 b .L${opcode}_continue
42 .L${opcode}_continue:
48 bgeu a2, a3, .L${opcode}_nsm # method not present in superclass
57 .L${opcode}_nsm:
|
| OP_SPUT_WIDE.S | 17 beqz a2, .L${opcode}_resolve # yes, do resolve
18 .L${opcode}_finish: # field ptr in a2, AA in rOBJ
21 GET_INST_OPCODE(rBIX) # extract opcode from rINST
39 .L${opcode}_resolve:
58 b .L${opcode}_finish # resume
|
| OP_EXECUTE_INLINE.S | 21 bnez a2, .L${opcode}_debugmode # yes - take slow path
22 .L${opcode}_resume:
27 BAL(.L${opcode}_continue) # make call; will return after
32 GET_INST_OPCODE(t0) # extract opcode from rINST
47 .L${opcode}_continue:
83 .L${opcode}_debugmode:
86 beqz v0, .L${opcode}_resume # did it resolve? no, just move on
95 BAL(.L${opcode}_continue) # make call; will return after
103 GET_INST_OPCODE(t0) # extract opcode from rINST
|
| OP_EXECUTE_INLINE_RANGE.S | 19 bnez a2, .L${opcode}_debugmode # yes - take slow path
20 .L${opcode}_resume:
24 BAL(.L${opcode}_continue) # make call; will return after
28 GET_INST_OPCODE(t0) # extract opcode from rINST
39 .L${opcode}_continue:
70 .L${opcode}_debugmode:
73 beqz v0, .L${opcode}_resume # did it resolve? no, just move on
83 BAL(.L${opcode}_continue) # make call; will return after
91 GET_INST_OPCODE(t0) # extract opcode from rINST
|
| /external/proguard/src/proguard/classfile/instruction/ |
| SwitchInstruction.java | 44 public SwitchInstruction(byte opcode,
48 this.opcode = opcode;
61 this.opcode = switchInstruction.opcode;
|
| /external/chromium/sdch/open-vcdiff/src/ |
| encodetable.cc | 107 // The VCDiff format allows each opcode to represent either
109 // examine the opcode generated by the last call to EncodeInstruction.
110 // If that opcode was a single-instruction opcode, this function checks
111 // whether there is a compound (double-instruction) opcode that can
114 // single-instruction opcode at position last_opcode_index_ will be
115 // overwritten with the new double-instruction opcode.
117 // In the majority of cases, no compound opcode will be possible,
118 // and a new single-instruction opcode will be appended to
120 // if the opcode does not implicitly give the instruction size
186 OpcodeOrNone opcode = kNoOpcode; local
[all...] |
| /external/chromium_org/sdch/open-vcdiff/src/ |
| encodetable.cc | 139 // The VCDiff format allows each opcode to represent either
141 // examine the opcode generated by the last call to EncodeInstruction.
142 // If that opcode was a single-instruction opcode, this function checks
143 // whether there is a compound (double-instruction) opcode that can
146 // single-instruction opcode at position last_opcode_index_ will be
147 // overwritten with the new double-instruction opcode.
149 // In the majority of cases, no compound opcode will be possible,
150 // and a new single-instruction opcode will be appended to
152 // if the opcode does not implicitly give the instruction size
218 OpcodeOrNone opcode = kNoOpcode; local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_pair_translate.c | 42 switch(inst->Opcode) {
48 inst->Opcode = RC_OPCODE_MAD;
70 inst->Opcode = RC_OPCODE_MAD;
75 inst->Opcode = RC_OPCODE_MAD;
99 switch(inst->Opcode) {
154 const struct rc_opcode_info * opcode; local
163 pair->RGB.Opcode = RC_OPCODE_REPL_ALPHA;
165 pair->RGB.Opcode = inst->Opcode;
170 pair->Alpha.Opcode = inst->Opcode
331 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode); local
361 const struct rc_opcode_info * opcode; local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_translate.c | 42 switch(inst->Opcode) {
48 inst->Opcode = RC_OPCODE_MAD;
70 inst->Opcode = RC_OPCODE_MAD;
75 inst->Opcode = RC_OPCODE_MAD;
99 switch(inst->Opcode) {
154 const struct rc_opcode_info * opcode; local
163 pair->RGB.Opcode = RC_OPCODE_REPL_ALPHA;
165 pair->RGB.Opcode = inst->Opcode;
170 pair->Alpha.Opcode = inst->Opcode
331 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode); local
361 const struct rc_opcode_info * opcode; local
[all...] |
| /external/open-vcdiff/src/ |
| encodetable.cc | 139 // The VCDiff format allows each opcode to represent either
141 // examine the opcode generated by the last call to EncodeInstruction.
142 // If that opcode was a single-instruction opcode, this function checks
143 // whether there is a compound (double-instruction) opcode that can
146 // single-instruction opcode at position last_opcode_index_ will be
147 // overwritten with the new double-instruction opcode.
149 // In the majority of cases, no compound opcode will be possible,
150 // and a new single-instruction opcode will be appended to
152 // if the opcode does not implicitly give the instruction size
218 OpcodeOrNone opcode = kNoOpcode; local
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| OP_CMPL_FLOAT.S | 45 bhi .L${opcode}_gt_or_nan @ C set and Z clear, disambiguate
48 .L${opcode}_finish:
52 GET_INST_OPCODE(ip) @ extract opcode from rINST
59 .L${opcode}_gt_or_nan:
65 bcc .L${opcode}_finish
67 b .L${opcode}_finish
81 bne ${opcode}_finish
86 b ${opcode}_continue
89 ${opcode}_continue:
91 bne ${opcode}_finis
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instruction.def | 26 #define HANDLE_TERM_INST(num, opcode, Class)
28 #define HANDLE_TERM_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
40 #define HANDLE_BINARY_INST(num, opcode, instclass)
42 #define HANDLE_BINARY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
54 #define HANDLE_MEMORY_INST(num, opcode, Class)
56 #define HANDLE_MEMORY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
68 #define HANDLE_CAST_INST(num, opcode, Class
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| Rop.java | 52 /** the opcode; one of the constants in {@link RegOps} */
53 private final int opcode; field in class:Rop
83 * @param opcode the opcode; one of the constants in {@link RegOps}
94 public Rop(int opcode, Type result, TypeList sources,
118 this.opcode = opcode;
131 * @param opcode the opcode; one of the constants in {@link RegOps}
141 public Rop(int opcode, Type result, TypeList sources
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| Rop.java | 52 /** the opcode; one of the constants in {@link RegOps} */
53 private final int opcode; field in class:Rop
83 * @param opcode the opcode; one of the constants in {@link RegOps}
94 public Rop(int opcode, Type result, TypeList sources,
118 this.opcode = opcode;
131 * @param opcode the opcode; one of the constants in {@link RegOps}
141 public Rop(int opcode, Type result, TypeList sources
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| Rop.java | 52 /** the opcode; one of the constants in {@link RegOps} */
53 private final int opcode; field in class:Rop
83 * @param opcode the opcode; one of the constants in {@link RegOps}
94 public Rop(int opcode, Type result, TypeList sources,
118 this.opcode = opcode;
131 * @param opcode the opcode; one of the constants in {@link RegOps}
141 public Rop(int opcode, Type result, TypeList sources
[all...] |
| /art/runtime/ |
| disassembler_arm.cc | 183 std::string opcode; local
191 opcode = "bkpt";
198 opcode = (((instruction >> 5) & 1) ? "blx" : "bx");
205 opcode = kDataProcessingOperations[op];
228 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : ""));
258 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a'));
265 opcode = (bl ? "bl" : "b");
272 opcode = "???";
275 opcode += kConditionCodeNames[cond];
276 opcode += suffixes
296 std::ostringstream opcode; local
1045 std::ostringstream opcode; local
[all...] |
| /external/smali/smali/src/main/antlr3/ |
| smaliTreeWalker.g | 865 throw new SemanticException(input, $I_REGISTER_LIST, "A list of registers can only have a maximum of 5 registers. Use the <op>/range alternate opcode instead.");
[all...] |
| /external/javassist/src/test/test/javassist/bytecode/analysis/ |
| ScannerTest.java | 13 import javassist.bytecode.Opcode;
118 /* 12 */ addJump(code, Opcode.GOTO, 125);
122 /* 20 */ addJump(code, Opcode.GOTO, 125);
124 /* 25 */ addJump(code, Opcode.JSR, 31);
126 /* 30 */ code.addOpcode(Opcode.ATHROW);
130 /* 33 */ code.addOpcode(Opcode.LOOKUPSWITCH);
139 /* 66 */ addJump(code, Opcode.GOTO, 111);
141 /* 71 */ addJump(code, Opcode.JSR, 77);
143 /* 76 */ code.add(Opcode.ATHROW);
148 /* 85 */ addJump(code, Opcode.GOTO, 106)
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /dalvik/vm/mterp/x86/ |
| OP_CHECK_CAST.S | 18 je .L${opcode}_okay # null obj, cast always succeeds
22 je .L${opcode}_resolve # no, go do it now
23 .L${opcode}_resolved:
25 jne .L${opcode}_fullcheck # no, do full check
26 .L${opcode}_okay:
37 .L${opcode}_fullcheck:
45 jne .L${opcode}_okay # no, success
62 .L${opcode}_resolve:
77 jmp .L${opcode}_resolved # pick up where we left off
|
| OP_INSTANCE_OF.S | 22 je .L${opcode}_store # null obj, not instance, store it
28 je .L${opcode}_resolve # not resolved, do it now
29 .L${opcode}_resolved: # eax<- obj->clazz, ecx<- resolved class
31 je .L${opcode}_trivial # yes, trivial finish
41 # fall through to ${opcode}_store
47 .L${opcode}_store:
59 .L${opcode}_trivial:
74 .L${opcode}_resolve:
93 jmp .L${opcode}_resolved
|
| /external/chromium_org/third_party/WebKit/Source/core/xml/ |
| XPathPredicate.h | 65 enum Opcode {
68 NumericOp(Opcode, PassOwnPtr<Expression> lhs, PassOwnPtr<Expression> rhs);
73 Opcode m_opcode;
78 enum Opcode { OP_EQ, OP_NE, OP_GT, OP_LT, OP_GE, OP_LE };
79 EqTestOp(Opcode, PassOwnPtr<Expression> lhs, PassOwnPtr<Expression> rhs);
85 Opcode m_opcode;
90 enum Opcode { OP_And, OP_Or };
91 LogicalOp(Opcode, PassOwnPtr<Expression> lhs, PassOwnPtr<Expression> rhs);
97 Opcode m_opcode;
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /external/proguard/src/proguard/optimize/peephole/ |
| ReachableCodeMarker.java | 118 byte opcode = simpleInstruction.opcode;
119 if (opcode == InstructionConstants.OP_IRETURN ||
120 opcode == InstructionConstants.OP_LRETURN ||
121 opcode == InstructionConstants.OP_FRETURN ||
122 opcode == InstructionConstants.OP_DRETURN ||
123 opcode == InstructionConstants.OP_ARETURN ||
124 opcode == InstructionConstants.OP_RETURN ||
125 opcode == InstructionConstants.OP_ATHROW)
139 if (variableInstruction.opcode == InstructionConstants.OP_RET
[all...] |
