| /dalvik/vm/mterp/x86/ |
| OP_IGET_WIDE.S | 22 jne .L${opcode}_finish # no, already resolved
33 jne .L${opcode}_finish
36 .L${opcode}_finish:
|
| OP_INVOKE_VIRTUAL.S | 20 jne .L${opcode}_continue # yes, continue
29 jne .L${opcode}_continue # no, continue
36 .L${opcode}_continue:
|
| OP_IPUT.S | 25 jne .L${opcode}_finish # no, already resolved
36 jne .L${opcode}_finish
39 .L${opcode}_finish:
|
| OP_IPUT_WIDE.S | 22 jne .L${opcode}_finish # no, already resolved
33 jne .L${opcode}_finish
36 .L${opcode}_finish:
|
| /external/chromium/sdch/open-vcdiff/src/ |
| codetablewriter_interface.h | 32 // Encode an ADD opcode with the "size" bytes starting at data
35 // Encode a COPY opcode with args "offset" (into dictionary) and "size" bytes.
38 // Encode a RUN opcode for "size" copies of the value "byte".
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_swizzle.h | 44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
|
| radeon_vert_fc.c | 105 new_inst->U.I.Opcode = RC_ME_PRED_SEQ;
125 new_inst->U.I.Opcode = RC_OPCODE_ADD;
139 inst->U.I.Opcode = RC_OPCODE_RCP;
145 inst->U.I.Opcode = RC_ME_PRED_SET_CLR;
159 new_inst->U.I.Opcode = RC_ME_PRED_SET_RESTORE;
182 if (inst->Next->U.I.Opcode == RC_OPCODE_BRK) {
188 inst->U.I.Opcode = RC_ME_PRED_SEQ;
191 inst->U.I.Opcode = RC_ME_PRED_SNEQ;
195 inst->U.I.Opcode = RC_VE_PRED_SNEQ_PUSH;
221 switch (inst->U.I.Opcode) {
[all...] |
| /external/kernel-headers/original/linux/can/ |
| bcm.h | 20 * @opcode: opcode, see enum below.
30 __u32 opcode; member in struct:bcm_msg_head
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 200 // Opcode is the opcode of an instruction that has an address operand,
202 // address that has displacement Offset. Return the opcode of a suitable
203 // instruction (which might be Opcode itself) or 0 if no such instruction
205 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
207 // If Opcode is a load instruction that has a LOAD AND TEST form,
208 // return the opcode for the testing form, otherwise return 0.
209 unsigned getLoadAndTest(unsigned Opcode) const;
217 // If Opcode is a COMPARE opcode for which an associated COMPARE AN
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_swizzle.h | 44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
|
| radeon_vert_fc.c | 105 new_inst->U.I.Opcode = RC_ME_PRED_SEQ;
125 new_inst->U.I.Opcode = RC_OPCODE_ADD;
139 inst->U.I.Opcode = RC_OPCODE_RCP;
145 inst->U.I.Opcode = RC_ME_PRED_SET_CLR;
159 new_inst->U.I.Opcode = RC_ME_PRED_SET_RESTORE;
182 if (inst->Next->U.I.Opcode == RC_OPCODE_BRK) {
188 inst->U.I.Opcode = RC_ME_PRED_SEQ;
191 inst->U.I.Opcode = RC_ME_PRED_SNEQ;
195 inst->U.I.Opcode = RC_VE_PRED_SNEQ_PUSH;
221 switch (inst->U.I.Opcode) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_fs.cpp | 57 this->opcode = BRW_OPCODE_NOP;
71 fs_inst::fs_inst(enum opcode opcode)
74 this->opcode = opcode;
77 fs_inst::fs_inst(enum opcode opcode, fs_reg dst)
80 this->opcode = opcode;
87 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs.cpp | 57 this->opcode = BRW_OPCODE_NOP;
71 fs_inst::fs_inst(enum opcode opcode)
74 this->opcode = opcode;
77 fs_inst::fs_inst(enum opcode opcode, fs_reg dst)
80 this->opcode = opcode;
87 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0
[all...] |
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 78 const char* GetTargetInstFmt(int opcode);
79 const char* GetTargetInstName(int opcode);
82 uint64_t GetTargetInstFlags(int opcode);
87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
95 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
100 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
102 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
104 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
106 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| FixedSizeInsn.java | 38 * @param opcode the opcode; one of the constants from {@link Dops}
44 public FixedSizeInsn(Dop opcode, SourcePosition position,
46 super(opcode, position, registers);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| FixedSizeInsn.java | 39 * @param opcode the opcode; one of the constants from {@link Dops}
45 public FixedSizeInsn(Dop opcode, SourcePosition position,
47 super(opcode, position, registers);
|
| /dalvik/dx/tests/071-dex-java-stack-ops/ |
| blort.j | 90 ; Test of "pop" opcode. This should end up causing a call to consume1(0).
101 ; Test of "pop2" opcode, form 1. This should end up causing a call
114 ; Test of "pop2" opcode, form 2. This should end up causing a call
126 ; Test of "dup" opcode. This should end up causing these calls in order:
138 ; Test of "dup_x1" opcode. This should end up causing these calls in order:
152 ; Test of "dup_x2" opcode, form 1. This should end up causing these calls
168 ; Test of "dup_x2" opcode, form 2. This should end up causing these calls
182 ; Test of "dup2" opcode, form 1. This should end up causing these calls
197 ; Test of "dup2" opcode, form 2. This should end up causing these calls
209 ; Test of "dup2_x1" opcode, form 1. This should end up causing these call
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| OP_ARRAY_LENGTH.S | 13 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_CONST_WIDE_32.S | 10 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_CONST_WIDE_HIGH16.S | 9 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_GOTO_16.S | 18 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_IPUT_OBJECT.S | 20 bne .L${opcode}_finish @ no, already resolved
26 bne .L${opcode}_finish @ yes, finish up
35 .L${opcode}_finish:
48 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_MONITOR_ENTER.S | 15 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_MOVE_RESULT_WIDE.S | 9 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
| OP_MOVE_WIDE_16.S | 11 GET_INST_OPCODE(ip) @ extract opcode from rINST
|
