| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| SparseSwitchPayloadDecodedInstruction.java | 38 int opcode, int[] keys, int[] targets) {
39 super(format, opcode, 0, null, 0, 0L);
|
| ThreeRegisterDecodedInstruction.java | 37 public ThreeRegisterDecodedInstruction(InstructionCodec format, int opcode,
40 super(format, opcode, index, indexType, target, literal);
|
| TwoRegisterDecodedInstruction.java | 34 public TwoRegisterDecodedInstruction(InstructionCodec format, int opcode,
37 super(format, opcode, index, indexType, target, literal);
|
| ZeroRegisterDecodedInstruction.java | 28 public ZeroRegisterDecodedInstruction(InstructionCodec format, int opcode,
30 super(format, opcode, index, indexType, target, literal);
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| ConservativeTranslationAdvice.java | 37 public boolean hasConstantOperation(Rop opcode,
43 public boolean requiresSourcesInOrder(Rop opcode,
|
| /external/javassist/src/main/javassist/convert/ |
| Transformer.java | 25 import javassist.bytecode.Opcode;
33 public abstract class Transformer implements Opcode {
|
| /external/kernel-headers/original/linux/ |
| ublock.h | 40 __u32 opcode; member in struct:ublock_in_header
45 __u32 opcode; member in struct:ublock_out_header
|
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugLine.cpp | 241 uint8_t opcode = debug_line_data.getU8(offset_ptr); local
243 if (opcode == 0) {
244 // Extended Opcodes always start with a zero opcode followed by
315 // Length doesn't include the zero opcode byte or the length itself, but
320 } else if (opcode < prologue->OpcodeBase) {
321 switch (opcode) {
371 // opcode 255. The motivation for DW_LNS_const_add_pc is this:
373 // small amount, it can use a single special opcode, which occupies
375 // twice the range of the last special opcode, it can use
376 // DW_LNS_const_add_pc followed by a special opcode, for a tota
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| stack-update-frame-opcode.ll | 11 ; Atoms use LEA to update the SP. Opcode bitness depends on data model.
12 ; Cores use sub/add to update the SP. Opcode bitness depends on data model.
|
| /external/mesa3d/src/gallium/docs/ |
| llvm-todo.txt | 7 TXQ opcode support - airlied WIP
8 TXF opcode support.
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 42 c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
119 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
122 for (i = 0; i < opcode->NumSrcRegs; ++i) {
127 if (opcode->HasDstReg) {
145 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
148 for(i = 0; i < opcode->NumSrcRegs; ++i) {
177 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
200 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
300 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
344 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| r3xx_vertprog.c | 375 const struct rc_opcode_info *info = rc_get_opcode_info(vpi->Opcode);
395 (vpi->Opcode != RC_OPCODE_SEQ &&
396 vpi->Opcode != RC_OPCODE_SNE));
398 switch (vpi->Opcode) {
511 rc_error(&compiler->Base, "Unknown opcode %s\n", info->Name);
568 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
570 for (i = 0; i < opcode->NumSrcRegs; ++i) {
577 if (opcode->HasDstReg) {
591 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode) local
626 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
667 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); local
706 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
812 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
827 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| radeonsi_pm4.c | 35 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
37 state->last_opcode = opcode;
58 unsigned opcode; local
61 opcode = PKT3_SET_CONFIG_REG;
65 opcode = PKT3_SET_SH_REG;
69 opcode = PKT3_SET_CONTEXT_REG;
78 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
79 si_pm4_cmd_begin(state, opcode);
|
| /external/mesa3d/src/glx/ |
| glx_query.c | 46 __glXQueryServerString(Display * dpy, int opcode, CARD32 screen, CARD32 name)
70 __glXGetString(Display * dpy, int opcode, CARD32 contextTag, CARD32 name)
119 __glXGetStringFromServer(Display * dpy, int opcode, CARD32 glxCode,
139 req->reqType = opcode;
164 __glXQueryServerString(Display * dpy, int opcode, CARD32 screen, CARD32 name)
166 return __glXGetStringFromServer(dpy, opcode,
171 __glXGetString(Display * dpy, int opcode, CARD32 contextTag, CARD32 name)
173 return __glXGetStringFromServer(dpy, opcode, X_GLsop_GetString,
|
| /external/proguard/src/proguard/classfile/editor/ |
| MethodInvocationFixer.java | 93 // Do we need to update the opcode?
94 byte opcode = constantInstruction.opcode;
100 if (opcode != InstructionConstants.OP_INVOKESTATIC)
121 if (opcode != InstructionConstants.OP_INVOKESPECIAL)
145 if (opcode != InstructionConstants.OP_INVOKEINTERFACE ||
169 if (opcode != InstructionConstants.OP_INVOKEVIRTUAL &&
170 (opcode != InstructionConstants.OP_INVOKESPECIAL ||
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| r3xx_vertprog.c | 375 const struct rc_opcode_info *info = rc_get_opcode_info(vpi->Opcode);
395 (vpi->Opcode != RC_OPCODE_SEQ &&
396 vpi->Opcode != RC_OPCODE_SNE));
398 switch (vpi->Opcode) {
511 rc_error(&compiler->Base, "Unknown opcode %s\n", info->Name);
568 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
570 for (i = 0; i < opcode->NumSrcRegs; ++i) {
577 if (opcode->HasDstReg) {
591 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode) local
626 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
667 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); local
706 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
812 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
827 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| FillArrayDataInsn.java | 45 * @param opcode {@code non-null;} the opcode
51 public FillArrayDataInsn(Rop opcode, SourcePosition position,
55 super(opcode, position, null, sources);
57 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
|
| Insn.java | 28 * an opcode (which specifies operation and source/result types), a
33 /** {@code non-null;} opcode */
34 private final Rop opcode; field in class:Insn
48 * @param opcode {@code non-null;} the opcode
53 public Insn(Rop opcode, SourcePosition position, RegisterSpec result,
55 if (opcode == null) {
56 throw new NullPointerException("opcode == null");
67 this.opcode = opcode;
[all...] |
| ThrowingInsn.java | 57 * @param opcode {@code non-null;} the opcode
62 public ThrowingInsn(Rop opcode, SourcePosition position,
65 super(opcode, position, null, sources);
67 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| DexTranslationAdvice.java | 57 public boolean hasConstantOperation(Rop opcode,
67 opcode.getOpcode() == RegOps.SUB) {
77 switch (opcode.getOpcode()) {
102 public boolean requiresSourcesInOrder(Rop opcode,
105 return !disableSourcesInOrder && opcode.isCallLike()
|
| FillArrayDataInsn.java | 44 * @param opcode {@code non-null;} the opcode
50 public FillArrayDataInsn(Rop opcode, SourcePosition position,
54 super(opcode, position, null, sources);
56 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
|
| Insn.java | 26 * an opcode (which specifies operation and source/result types), a
31 /** {@code non-null;} opcode */
32 private final Rop opcode; field in class:Insn
46 * @param opcode {@code non-null;} the opcode
51 public Insn(Rop opcode, SourcePosition position, RegisterSpec result,
53 if (opcode == null) {
54 throw new NullPointerException("opcode == null");
65 this.opcode = opcode;
[all...] |
| ThrowingInsn.java | 57 * @param opcode {@code non-null;} the opcode
62 public ThrowingInsn(Rop opcode, SourcePosition position,
65 super(opcode, position, null, sources);
67 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
|
| /dalvik/vm/compiler/codegen/arm/ |
| ArchFactory.cpp | 106 static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpcode opcode)
118 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
119 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
121 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
122 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
|
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_opt_constant_fold.c | 139 switch (inst->Opcode) {
154 inst->Opcode = OPCODE_MOV;
184 inst->Opcode = OPCODE_MOV;
209 * the opcode results in various failures of the loop control.
213 if (inst->Opcode >= OPCODE_DP3)
216 if (inst->Opcode == OPCODE_DP4)
219 inst->Opcode = OPCODE_MOV;
243 inst->Opcode = OPCODE_MOV;
267 inst->Opcode = OPCODE_MOV;
275 inst->Opcode = OPCODE_MOV
[all...] |
