| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| DexTranslationAdvice.java | 57 public boolean hasConstantOperation(Rop opcode,
67 opcode.getOpcode() == RegOps.SUB) {
77 switch (opcode.getOpcode()) {
102 public boolean requiresSourcesInOrder(Rop opcode,
105 return !disableSourcesInOrder && opcode.isCallLike()
|
| FillArrayDataInsn.java | 45 * @param opcode {@code non-null;} the opcode
51 public FillArrayDataInsn(Rop opcode, SourcePosition position,
55 super(opcode, position, null, sources);
57 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
|
| Insn.java | 26 * an opcode (which specifies operation and source/result types), a
31 /** {@code non-null;} opcode */
32 private final Rop opcode; field in class:Insn
46 * @param opcode {@code non-null;} the opcode
51 public Insn(Rop opcode, SourcePosition position, RegisterSpec result,
53 if (opcode == null) {
54 throw new NullPointerException("opcode == null");
65 this.opcode = opcode;
[all...] |
| ThrowingInsn.java | 57 * @param opcode {@code non-null;} the opcode
62 public ThrowingInsn(Rop opcode, SourcePosition position,
65 super(opcode, position, null, sources);
67 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
|
| /external/javassist/src/main/javassist/bytecode/ |
| Mnemonic.java | 21 * <p>This interface has been separated from javassist.bytecode.Opcode
23 * interface were merged with Opcode, extra memory would be unnecessary
26 * @see Opcode
31 * The instruction names (mnemonics) sorted by the opcode.
37 String[] OPCODE = {
|
| /external/mesa3d/src/mesa/program/ |
| prog_opt_constant_fold.c | 139 switch (inst->Opcode) {
154 inst->Opcode = OPCODE_MOV;
184 inst->Opcode = OPCODE_MOV;
209 * the opcode results in various failures of the loop control.
213 if (inst->Opcode >= OPCODE_DP3)
216 if (inst->Opcode == OPCODE_DP4)
219 inst->Opcode = OPCODE_MOV;
243 inst->Opcode = OPCODE_MOV;
267 inst->Opcode = OPCODE_MOV;
275 inst->Opcode = OPCODE_MOV
[all...] |
| /external/proguard/src/proguard/classfile/instruction/ |
| LookUpSwitchInstruction.java | 47 public LookUpSwitchInstruction(byte opcode,
52 this.opcode = opcode;
66 this.opcode = lookUpSwitchInstruction.opcode;
|
| TableSwitchInstruction.java | 48 public TableSwitchInstruction(byte opcode,
54 this.opcode = opcode;
69 this.opcode = tableSwitchInstruction.opcode;
|
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 113 int dalvik_offset; // Offset of Dalvik opcode.
117 int opcode; member in struct:art::LIR
167 #define is_pseudo_opcode(opcode) (static_cast<int>(opcode) < 0)
174 int vaddr; // Dalvik offset of switch opcode.
183 int vaddr; // Dalvik offset of FILL_ARRAY_DATA opcode.
262 LIR* RawLIR(int dalvik_offset, int opcode, int op0 = 0, int op1 = 0,
264 LIR* NewLIR0(int opcode);
265 LIR* NewLIR1(int opcode, int dest);
266 LIR* NewLIR2(int opcode, int dest, int src1)
[all...] |
| local_optimizations.cc | 81 if (is_pseudo_opcode(this_lir->opcode)) {
87 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode);
102 native_reg_id = (GetTargetInstFlags(this_lir->opcode) & IS_STORE) ? this_lir->operands[2]
107 bool is_this_lir_load = GetTargetInstFlags(this_lir->opcode) & IS_LOAD;
139 if (check_lir->flags.is_nop || is_pseudo_opcode(check_lir->opcode)) {
150 uint64_t check_flags = GetTargetInstFlags(check_lir->opcode);
242 uint64_t flags = GetTargetInstFlags(check_lir->opcode);
289 if (is_pseudo_opcode(this_lir->opcode)) {
293 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode);
366 if (stop_here || !is_pseudo_opcode(check_lir->opcode)) {
[all...] |
| /external/bluetooth/bluedroid/stack/include/ |
| avrc_defs.h | 57 by the opcode and operand,
61 opcode but cannot respond because the current state
98 #define AVRC_OP_PASS_THRU 0x7C /* panel subunit opcode */
764 UINT8 opcode; \/* Op Code (passthrough, vendor, etc) *\/ member in struct:__anon890
970 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon908
979 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon909
988 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon910
998 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon911
1008 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon912
1018 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon913
1029 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon914
1039 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon915
1048 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon916
1058 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon917
1068 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon918
1077 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon919
1086 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon920
1095 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon921
1108 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon922
1119 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon923
1132 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon924
1141 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon925
1152 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon926
1162 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon927
1170 UINT8 opcode; \/* Op Code (assigned by AVRC_BldCommand according to pdu) *\/ member in struct:__anon928
1209 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon930
1220 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon931
1230 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon932
1240 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon933
1250 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon934
1260 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon935
1270 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon936
1313 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon940
1323 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon941
1332 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon942
1345 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon943
1356 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon944
1365 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon945
1375 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon946
1385 UINT8 opcode; \/* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) *\/ member in struct:__anon947
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 160 /// OperandAllocator - Pool allocation for machine-opcode SDNode operands.
551 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
552 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
553 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2);
554 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
556 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
558 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
561 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
563 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
565 SDValue getNode(unsigned Opcode, SDLoc DL
[all...] |
| FastISel.h | 104 bool SelectOperator(const User *I, unsigned Opcode);
181 /// instruction with the given type and opcode be emitted.
184 unsigned Opcode);
187 /// instruction with the given type, opcode, and register operand be emitted.
190 unsigned Opcode,
194 /// instruction with the given type, opcode, and register operands be emitted.
197 unsigned Opcode,
202 /// instruction with the given type, opcode, and register and immediate
206 unsigned Opcode,
211 /// instruction with the given type, opcode, and register and floating-poin
[all...] |
| /external/chromium_org/net/websockets/ |
| websocket_frame.cc | 45 scoped_ptr<WebSocketFrameHeader> ret(new WebSocketFrameHeader(opcode));
55 opcode = source.opcode;
60 WebSocketFrame::WebSocketFrame(WebSocketFrameHeader::OpCode opcode)
61 : header(opcode) {}
86 DCHECK((header.opcode & kOpCodeMask) == header.opcode)
87 << "header.opcode must fit to kOpCodeMask.";
114 first_byte |= header.opcode & kOpCodeMask
[all...] |
| websocket_basic_stream.cc | 294 const WebSocketFrameHeader::OpCode opcode = current_frame_header_->opcode; local
295 if (WebSocketFrameHeader::IsKnownControlOpCode(opcode)) {
298 DVLOG(1) << "WebSocket protocol error. Control frame, opcode=" << opcode
303 DVLOG(1) << "WebSocket protocol error. Control frame, opcode=" << opcode
313 DVLOG(2) << "Encountered a split control frame, opcode " << opcode;
367 const WebSocketFrameHeader::OpCode opcode = current_frame_header_->opcode; local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 73 reader_data->Writer->U.I.PreSub.Opcode,
93 (inst->U.I.Opcode == RC_OPCODE_TEX ||
94 inst->U.I.Opcode == RC_OPCODE_TXB ||
95 inst->U.I.Opcode == RC_OPCODE_TXP ||
96 inst->U.I.Opcode == RC_OPCODE_TXD ||
97 inst->U.I.Opcode == RC_OPCODE_TXL ||
98 inst->U.I.Opcode == RC_OPCODE_KIL)){
217 inst->U.I.Opcode = RC_OPCODE_MUL;
224 inst->U.I.Opcode = RC_OPCODE_ADD;
230 inst->U.I.Opcode = RC_OPCODE_MOV
311 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 73 reader_data->Writer->U.I.PreSub.Opcode,
93 (inst->U.I.Opcode == RC_OPCODE_TEX ||
94 inst->U.I.Opcode == RC_OPCODE_TXB ||
95 inst->U.I.Opcode == RC_OPCODE_TXP ||
96 inst->U.I.Opcode == RC_OPCODE_TXD ||
97 inst->U.I.Opcode == RC_OPCODE_TXL ||
98 inst->U.I.Opcode == RC_OPCODE_KIL)){
217 inst->U.I.Opcode = RC_OPCODE_MUL;
224 inst->U.I.Opcode = RC_OPCODE_ADD;
230 inst->U.I.Opcode = RC_OPCODE_MOV
311 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
| tgsi_ureg.h | 465 /* Generic instruction emitter. Use if you need to pass the opcode as
470 unsigned opcode,
479 unsigned opcode,
491 unsigned opcode,
508 unsigned opcode,
549 unsigned opcode = TGSI_OPCODE_##op; \
551 opcode, \
568 unsigned opcode = TGSI_OPCODE_##op; \
570 opcode, \
588 unsigned opcode = TGSI_OPCODE_##op;
[all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 95 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
100 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
102 virtual unsigned getCFInstrCost(unsigned Opcode) const;
103 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
105 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
107 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
218 unsigned BasicTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
223 int ISD = TLI->InstructionOpcodeToISD(Opcode);
224 assert(ISD && "Invalid opcode");
252 unsigned Cost = TopTTI->getArithmeticInstrCost(Opcode, Ty->getScalarType())
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_ureg.h | 465 /* Generic instruction emitter. Use if you need to pass the opcode as
470 unsigned opcode,
479 unsigned opcode,
491 unsigned opcode,
508 unsigned opcode,
549 unsigned opcode = TGSI_OPCODE_##op; \
551 opcode, \
568 unsigned opcode = TGSI_OPCODE_##op; \
570 opcode, \
588 unsigned opcode = TGSI_OPCODE_##op;
[all...] |
| /dalvik/vm/mterp/ |
| README.txt | 12 development of platform-specific code one opcode at a time.
67 be done via table-start-address + (opcode * handler-size). With
93 performed on the opcode name. This command is not applicable to
104 Indicates the start of the opcode list. Must precede any "op"
108 op <opcode> <directory>
111 default source file location of the specified opcode. The opcode
116 alt <opcode> <directory>
120 in the alternate handler table. The opcode definition will come from
127 Indicates the end of the opcode list. All kNumPackedOpcode
[all...] |
| /external/llvm/utils/TableGen/ |
| X86DisassemblerTables.h | 35 /// The decoder tables. There is one for each opcode type:
132 /// Opcode and ModRMDecisions. A ContextDecision is printed as:
148 /// IC is one of the contexts in InstructionContext. There is an opcode
190 /// 0xnn is the lowest possible opcode for the current instruction, used for
234 /// @param opcode - The opcode of the instruction, for error reporting.
238 uint8_t opcode);
250 /// setTableFields - Uses the opcode type, instruction context, opcode, and a
254 /// @param type - The opcode type (ONEBYTE, TWOBYTE, etc.
[all...] |
| /external/chromium/sdch/open-vcdiff/src/ |
| encodetable_test.cc | 56 int opcode) {
57 g_exercise_code_table_->inst1[opcode] = inst1;
58 g_exercise_code_table_->mode1[opcode] = mode1;
59 g_exercise_code_table_->size1[opcode] = (inst1 == VCD_NOOP) ? 0 : size1;
60 g_exercise_code_table_->inst2[opcode] = inst2;
61 g_exercise_code_table_->mode2[opcode] = mode2;
62 g_exercise_code_table_->size2[opcode] = (inst2 == VCD_NOOP) ? 0 : size2;
67 int opcode = 0; local
86 AddExerciseOpcode(inst1, mode1, 0, inst2, mode2, 0, opcode++);
87 AddExerciseOpcode(inst1, mode1, 0, inst2, mode2, 255, opcode++)
[all...] |
| /external/chromium_org/sdch/open-vcdiff/src/ |
| encodetable_test.cc | 55 int opcode) {
56 g_exercise_code_table_->inst1[opcode] = inst1;
57 g_exercise_code_table_->mode1[opcode] = mode1;
58 g_exercise_code_table_->size1[opcode] = (inst1 == VCD_NOOP) ? 0 : size1;
59 g_exercise_code_table_->inst2[opcode] = inst2;
60 g_exercise_code_table_->mode2[opcode] = mode2;
61 g_exercise_code_table_->size2[opcode] = (inst2 == VCD_NOOP) ? 0 : size2;
66 int opcode = 0; local
85 AddExerciseOpcode(inst1, mode1, 0, inst2, mode2, 0, opcode++);
86 AddExerciseOpcode(inst1, mode1, 0, inst2, mode2, 255, opcode++)
[all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/objfmts/coff/ |
| win64-except.c | 363 switch (code->opcode) {
372 code->opcode = UWOP_ALLOC_SMALL;
379 code->opcode = UWOP_SAVE_NONVOL;
389 code->opcode = UWOP_SAVE_XMM128;
397 yasm_internal_error(N_("unrecognied unwind opcode"));
435 if (code->opcode == UWOP_ALLOC_LARGE && code->info == 1)
438 if (code->opcode == UWOP_ALLOC_SMALL && new_val > 128) {
440 code->opcode = UWOP_ALLOC_LARGE;
451 } else if (code->opcode == UWOP_SAVE_NONVOL && span == 2) {
452 code->opcode = UWOP_SAVE_NONVOL_FAR
[all...] |
