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  /dalvik/vm/mterp/mips/
OP_IPUT_OBJECT_QUICK.S 20 GET_INST_OPCODE(t0) # extract opcode from rINST
OP_IPUT_WIDE_QUICK.S 15 GET_INST_OPCODE(t0) # extract opcode from rINST
OP_MONITOR_EXIT.S 22 GET_INST_OPCODE(t0) # extract opcode from rINST
OP_MUL_LONG_2ADDR.S 24 GET_INST_OPCODE(t1) # extract opcode from rINST
unop.S 17 GET_INST_OPCODE(t1) # extract opcode from rINST
unopWide.S 18 GET_INST_OPCODE(t0) # extract opcode from rINST
unopWider.S 17 GET_INST_OPCODE(t0) # extract opcode from rINST
  /dalvik/vm/mterp/x86/
OP_AGET.S 20 .L${opcode}_finish:
OP_APUT.S 20 .L${opcode}_finish:
  /external/chromium_org/third_party/WebKit/Source/modules/websockets/
MainThreadWebSocketChannel.cpp 539 if (WebSocketFrame::isReservedOpCode(frame.opCode)) {
540 failAsError("Unrecognized frame opcode: " + String::number(frame.opCode));
555 if (WebSocketFrame::isControlOpCode(frame.opCode) && !frame.final) {
556 failAsError("Received fragmented control frame: opcode = " + String::number(frame.opCode));
562 if (WebSocketFrame::isControlOpCode(frame.opCode) && WebSocketFrame::needsExtendedLengthField(frame.payloadLength)) {
569 if (m_hasContinuousFrame && frame.opCode != WebSocketFrame::OpCodeContinuation && !WebSocketFrame::isControlOpCode(frame.opCode)) {
576 switch (frame.opCode) {
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  /external/chromium_org/third_party/skia/src/animator/
SkScriptRuntime.h 34 bool executeTokens(unsigned char* opCode);
  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
jmpfar.asm 16 ;mov ax, 1234:5678 ; YASM: immediate does not support segment; NASM: invalid combination of opcode and operands
  /external/llvm/lib/Target/R600/
R600ControlFlowFinalizer.cpp 67 unsigned Opcode = 0;
71 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
74 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600;
77 Opcode = isEg ? AMDGPU::CF_CALL_FS_EG : AMDGPU::CF_CALL_FS_R600;
80 Opcode = isEg ? AMDGPU::WHILE_LOOP_EG : AMDGPU::WHILE_LOOP_R600;
83 Opcode = isEg ? AMDGPU::END_LOOP_EG : AMDGPU::END_LOOP_R600;
86 Opcode = isEg ? AMDGPU::LOOP_BREAK_EG : AMDGPU::LOOP_BREAK_R600;
89 Opcode = isEg ? AMDGPU::CF_CONTINUE_EG : AMDGPU::CF_CONTINUE_R600;
92 Opcode = isEg ? AMDGPU::CF_JUMP_EG : AMDGPU::CF_JUMP_R600;
95 Opcode = isEg ? AMDGPU::CF_ELSE_EG : AMDGPU::CF_ELSE_R600
    [all...]
  /external/llvm/lib/Target/XCore/
XCoreFrameLowering.cpp 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
70 BuildMI(MBB, I, dl, TII.get(Opcode))
122 int Opcode;
124 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
128 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
225 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
226 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
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  /external/llvm/test/TableGen/
defmclass.td 16 bits<4> opcode = op;
  /external/proguard/src/proguard/optimize/peephole/
BranchTargetFinder.java 457 byte opcode = simpleInstruction.opcode;
458 if (opcode == InstructionConstants.OP_IRETURN ||
459 opcode == InstructionConstants.OP_LRETURN ||
460 opcode == InstructionConstants.OP_FRETURN ||
461 opcode == InstructionConstants.OP_DRETURN ||
462 opcode == InstructionConstants.OP_ARETURN ||
463 opcode == InstructionConstants.OP_ATHROW)
483 if (constantInstruction.opcode == InstructionConstants.OP_NEW)
523 if (variableInstruction.opcode == InstructionConstants.OP_RET
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  /external/skia/src/animator/
SkScriptRuntime.h 34 bool executeTokens(unsigned char* opCode);
  /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/
MethodDefinition.java 43 import org.jf.dexlib.Code.Opcode;
80 if (instruction.opcode == Opcode.PACKED_SWITCH) {
85 } else if (instruction.opcode == Opcode.SPARSE_SWITCH) {
246 if (instructions[index].opcode == Opcode.NOP) {
261 if (instructions[index].opcode == Opcode.NOP) {
276 if (instruction.getInstruction().opcode != Opcode.NOP |
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  /external/tcpdump/
igrp.h 7 u_int8_t ig_vop; /* protocol version number / opcode */
  /external/v8/src/x64/
disasm-x64.cc 424 const char* TwoByteMnemonic(byte opcode);
1016 byte opcode = *(data + 1); local
1019 const char* mnemonic = TwoByteMnemonic(opcode);
1023 if (opcode == 0x3A) {
1044 if (opcode == 0x1f) {
1055 } else if (opcode == 0x28) {
1058 } else if (opcode == 0x29) {
1062 } else if (opcode == 0x6E) {
1067 } else if (opcode == 0x6F) {
1071 } else if (opcode == 0x7E)
1591 byte opcode = *data; local
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  /hardware/qcom/bt/libbt-vendor/src/
hardware.c 113 uint16_t opcode; local
117 STREAM_TO_UINT16(opcode,p);
119 ALOGI("%s Opcode:0x%04X Status: %d", __FUNCTION__, opcode, status);
  /art/compiler/dex/quick/mips/
assemble_mips.cc 26 * opcode: MipsOpCode enum
27 * skeleton: pre-designated bit-pattern for this opcode
41 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \
44 {k3, k3s, k3e}}, opcode, flags, name, fmt, size}
463 int opcode = lir->opcode; local
465 switch (opcode) {
471 case kMipsBeq: opcode = kMipsBne; break;
472 case kMipsBne: opcode = kMipsBeq; break;
473 case kMipsBeqz: opcode = kMipsBnez; break
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  /dalvik/dx/src/com/android/dx/io/instructions/
FiveRegisterDecodedInstruction.java 43 public FiveRegisterDecodedInstruction(InstructionCodec format, int opcode,
46 super(format, opcode, index, indexType, target, literal);
FourRegisterDecodedInstruction.java 40 public FourRegisterDecodedInstruction(InstructionCodec format, int opcode,
43 super(format, opcode, index, indexType, target, literal);
  /dalvik/libdex/
DexOpcodes.cpp 18 * Table of Dalvik opcode names.
21 * automatically by the opcode-gen tool. Any edits to the generated
29 * Dalvik opcode names.
32 // BEGIN(libdex-opcode-names); GENERATED AUTOMATICALLY BY opcode-gen
289 // END(libdex-opcode-names)
293 * Return the name of an opcode.
295 const char* dexGetOpcodeName(Opcode op)

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