| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_CMPL_DOUBLE.S | 21 bhi .L${opcode}_gt_or_nan @ C set and Z clear, disambiguate
30 .L${opcode}_gt_or_nan:
|
| /dalvik/vm/mterp/armv5te/ |
| OP_INVOKE_STATIC.S | 22 b .L${opcode}_resolve
26 .L${opcode}_resolve:
|
| /dalvik/vm/mterp/mips/ |
| OP_INVOKE_STATIC.S | 22 b .L${opcode}_resolve
25 .L${opcode}_resolve:
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/windows/ |
| mini_disassembler.h | 57 // assembly parameters. The name of the opcode (as a string) is given,
62 // -# Indicates if opcode is a jump (any kind) or a return (any kind)
66 // -# The opcode length is always calculated, so that the patching utility
101 // opcode. In the last two (error) cases, cbInstruction will be set
118 // operand_bytes_ if any are specifies by the opcode directly.
119 // @return Number of opcode bytes.
142 // The instruction type we have decoded from the opcode.
175 // Huge big opcode table based on the IA-32 manual, defined
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/windows/ |
| mini_disassembler.h | 57 // assembly parameters. The name of the opcode (as a string) is given,
62 // -# Indicates if opcode is a jump (any kind) or a return (any kind)
66 // -# The opcode length is always calculated, so that the patching utility
101 // opcode. In the last two (error) cases, cbInstruction will be set
118 // operand_bytes_ if any are specifies by the opcode directly.
119 // @return Number of opcode bytes.
142 // The instruction type we have decoded from the opcode.
175 // Huge big opcode table based on the IA-32 manual, defined
|
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| FiveRegisterDecodedInstruction.java | 43 public FiveRegisterDecodedInstruction(InstructionCodec format, int opcode,
46 super(format, opcode, index, indexType, target, literal);
|
| FourRegisterDecodedInstruction.java | 40 public FourRegisterDecodedInstruction(InstructionCodec format, int opcode,
43 super(format, opcode, index, indexType, target, literal);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.cpp | 10 // This file implements the unwind opcode assmebler for ARM exception handling
57 /// Fill the rest of bytes with FINISH opcode.
69 // One byte opcode to save register r14 and r11-r4
71 // The one byte opcode will always save r4, thus we can't use the one byte
72 // opcode when r4 is not in .save directive.
84 // Emit this opcode when the mask covers every registers.
97 // Two bytes opcode to save register r15-r4
101 // Opcode to save register r3-r0
|
| /external/proguard/src/proguard/classfile/instruction/ |
| InstructionFactory.java | 39 byte opcode = code[index++];
42 if (opcode == InstructionConstants.OP_WIDE)
44 opcode = code[index++];
48 switch (opcode)
290 throw new IllegalArgumentException("Unknown instruction opcode ["+opcode+"] at offset "+offset);
293 instruction.opcode = opcode;
|
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| UnknownInstruction.java | 34 import org.jf.dexlib.Code.Opcode;
40 super(Opcode.NOP);
|
| /packages/apps/Stk/src/com/android/stk/ |
| StkCmdReceiver.java | 45 args.putInt(StkAppService.OPCODE, StkAppService.OP_CMD);
54 args.putInt(StkAppService.OPCODE, StkAppService.OP_END_SESSION);
|
| /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/ |
| x86_64-xlate.pl | 104 { package opcode; # pick up opcodes
228 die if (opcode->mnemonic() ne "mov");
229 opcode->mnemonic("lea");
275 $sz="q" if ($self->{asterisk} || opcode->mnemonic() eq "movq");
276 $sz="l" if (opcode->mnemonic() eq "movd");
416 if ($nasm && opcode->mnemonic()=~m/^j/) {
429 my %opcode = # lea 2f-1f(%rip),%dst; 1: nop; 2:
448 $line=sprintf "0x%x,0x90000000",$opcode{$1};
654 local *opcode=shift;
659 push @opcode,($rex|0x40) if ($rex)
[all...] |
| /external/openssl/crypto/perlasm/ |
| x86_64-xlate.pl | 104 { package opcode; # pick up opcodes
228 die if (opcode->mnemonic() ne "mov");
229 opcode->mnemonic("lea");
275 $sz="q" if ($self->{asterisk} || opcode->mnemonic() eq "movq");
276 $sz="l" if (opcode->mnemonic() eq "movd");
416 if ($nasm && opcode->mnemonic()=~m/^j/) {
429 my %opcode = # lea 2f-1f(%rip),%dst; 1: nop; 2:
448 $line=sprintf "0x%x,0x90000000",$opcode{$1};
654 local *opcode=shift;
659 push @opcode,($rex|0x40) if ($rex)
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 84 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,
90 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,
96 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,
102 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,
108 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,
114 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,
120 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,
126 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,
249 #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \
250 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" },
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| CstInsn.java | 47 * @param opcode the opcode; one of the constants from {@link Dops}
54 public CstInsn(Dop opcode, SourcePosition position,
56 super(opcode, position, registers);
69 public DalvInsn withOpcode(Dop opcode) {
71 new CstInsn(opcode, getPosition(), getRegisters(), constant);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| CstInsn.java | 47 * @param opcode the opcode; one of the constants from {@link Dops}
54 public CstInsn(Dop opcode, SourcePosition position,
56 super(opcode, position, registers);
69 public DalvInsn withOpcode(Dop opcode) {
71 new CstInsn(opcode, getPosition(), getRegisters(), constant);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| CstInsn.java | 47 * @param opcode the opcode; one of the constants from {@link Dops}
54 public CstInsn(Dop opcode, SourcePosition position,
56 super(opcode, position, registers);
69 public DalvInsn withOpcode(Dop opcode) {
71 new CstInsn(opcode, getPosition(), getRegisters(), constant);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
20 switch (Opcode) {
46 llvm_unreachable("Unknown PPC branch opcode!");
49 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) {
50 switch (Opcode) {
76 llvm_unreachable("Unknown PPC branch opcode!");
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCAsmBackend.cpp | 38 // If Opcode is a relaxable interprocedural reference, return the relaxed form,
40 static unsigned getRelaxedOpcode(unsigned Opcode) {
41 switch (Opcode) {
133 unsigned Opcode = getRelaxedOpcode(Inst.getOpcode());
134 assert(Opcode && "Unexpected insn to relax");
136 Res.setOpcode(Opcode);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/proguard/src/proguard/classfile/editor/ |
| InstructionWriter.java | 85 new ConstantInstruction(constantInstruction.opcode,
110 new VariableInstruction(variableInstruction.opcode,
139 switch (branchInstruction.opcode)
145 new BranchInstruction(branchInstruction.opcode,
169 new BranchInstruction((byte)(((branchInstruction.opcode+1) ^ 1) - 1),
183 new BranchInstruction((byte)(branchInstruction.opcode ^ 1),
|
| /prebuilts/gcc/darwin-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/ |
| tree-ssa-sccvn.h | 32 opcode, and a type. Result is the value number of the operation,
40 ENUM_BITFIELD(tree_code) opcode : 16; member in struct:vn_nary_op_s
67 They consist of an opcode, type, and some number of operands. For
68 a given opcode, some, all, or none of the operands may be used.
70 portion of the addressing calculation that opcode performs. */
74 enum tree_code opcode; member in struct:vn_reference_op_struct
|
| /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/ |
| tree-ssa-sccvn.h | 32 opcode, and a type. Result is the value number of the operation,
40 ENUM_BITFIELD(tree_code) opcode : 16; member in struct:vn_nary_op_s
67 They consist of an opcode, type, and some number of operands. For
68 a given opcode, some, all, or none of the operands may be used.
70 portion of the addressing calculation that opcode performs. */
74 enum tree_code opcode; member in struct:vn_reference_op_struct
|
| /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/ |
| tree-ssa-sccvn.h | 32 opcode, and a type. Result is the value number of the operation,
40 ENUM_BITFIELD(tree_code) opcode : 16; member in struct:vn_nary_op_s
67 They consist of an opcode, type, and some number of operands. For
68 a given opcode, some, all, or none of the operands may be used.
70 portion of the addressing calculation that opcode performs. */
74 enum tree_code opcode; member in struct:vn_reference_op_struct
|
