| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/ |
| r300_vs_draw.c | 246 if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
249 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
261 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
291 /* Inserting 2 instructions before the END opcode moves all following
292 * labels by 2. Subroutines are always after the END opcode so
294 if (inst->Instruction.Opcode == TGSI_OPCODE_CAL) {
298 * the END opcode. */
300 (inst->Instruction.Opcode == TGSI_OPCODE_IF ||
301 inst->Instruction.Opcode == TGSI_OPCODE_ELSE ||
302 inst->Instruction.Opcode == TGSI_OPCODE_BGNLOOP |
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 95 bool R600InstrInfo::isMov(unsigned Opcode) const
99 switch(Opcode) {
110 // an opcode falls into this category.
111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const
113 switch (Opcode) {
122 bool R600InstrInfo::isReductionOp(unsigned Opcode) const
124 switch(Opcode) {
132 bool R600InstrInfo::isCubeOp(unsigned Opcode) const
134 switch(Opcode) {
152 isPredicateSetter(unsigned Opcode)
[all...] |
| /external/javassist/src/main/javassist/bytecode/analysis/ |
| Analyzer.java | 31 import javassist.bytecode.Opcode;
85 public class Analyzer implements Opcode {
182 int opcode = iter.byteAt(pos); local
184 if (opcode == TABLESWITCH) {
186 } else if (opcode == LOOKUPSWITCH) {
188 } else if (opcode == RET) {
190 } else if (Util.isJumpInstruction(opcode)) {
193 if (Util.isJsr(opcode)) {
196 } else if (! Util.isGoto(opcode)) {
201 } else if (opcode != ATHROW && ! Util.isReturn(opcode))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 42 // if there is not such an opcode.
296 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
298 bool isFpMLxInstruction(unsigned Opcode) const {
299 return MLxEntryMap.count(Opcode);
302 /// isFpMLxInstruction - This version also returns the multiply opcode and the
303 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
305 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
309 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
312 bool canCauseFpMLxStall(unsigned Opcode) const {
313 return MLxHazardOpcodes.count(Opcode);
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_vs_draw.c | 246 if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
249 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
261 new_inst.Instruction.Opcode = TGSI_OPCODE_MOV;
291 /* Inserting 2 instructions before the END opcode moves all following
292 * labels by 2. Subroutines are always after the END opcode so
294 if (inst->Instruction.Opcode == TGSI_OPCODE_CAL) {
298 * the END opcode. */
300 (inst->Instruction.Opcode == TGSI_OPCODE_IF ||
301 inst->Instruction.Opcode == TGSI_OPCODE_ELSE ||
302 inst->Instruction.Opcode == TGSI_OPCODE_BGNLOOP |
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 95 bool R600InstrInfo::isMov(unsigned Opcode) const
99 switch(Opcode) {
110 // an opcode falls into this category.
111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const
113 switch (Opcode) {
122 bool R600InstrInfo::isReductionOp(unsigned Opcode) const
124 switch(Opcode) {
132 bool R600InstrInfo::isCubeOp(unsigned Opcode) const
134 switch(Opcode) {
152 isPredicateSetter(unsigned Opcode)
[all...] |
| /dalvik/vm/mterp/ |
| gen-mterp.py | 25 interp_defs_file = "../../libdex/DexOpcodes.h" # need opcode list
143 # Start of opcode list.
157 # Set location of a single alt opcode's source file.
168 raise DataParseError("unknown opcode %s" % tokens[1])
177 # Set location of a single opcode's source file.
188 raise DataParseError("unknown opcode %s" % tokens[1])
204 dict.update({ "opcode":op, "opnum":i })
206 "_%(opcode)s /* 0x%(opnum)02x */\n" % dict)
210 # End of opcode list; emit instruction blocks.
259 raise SyntaxError, "bad opcode count
[all...] |
| /external/bluetooth/bluedroid/stack/avrc/ |
| avrc_bld_tg.c | 730 UINT8 opcode = avrc_opcode_from_pdu(p_rsp->pdu); local
732 AVRC_TRACE_API3("avrc_bld_init_rsp_buffer: pdu=%x, opcode=%x/%x", p_rsp->pdu, opcode,
733 p_rsp->rsp.opcode);
734 if (opcode != p_rsp->rsp.opcode && p_rsp->rsp.status != AVRC_STS_NO_ERROR &&
735 avrc_is_valid_opcode(p_rsp->rsp.opcode))
737 opcode = p_rsp->rsp.opcode;
738 AVRC_TRACE_API1("opcode=%x", opcode)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_vec4_emit.cpp | 264 brw_math_function(inst->opcode),
292 brw_math_function(inst->opcode),
308 brw_math_function(inst->opcode),
327 brw_math_function(inst->opcode),
347 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
359 brw_math_function(inst->opcode),
374 switch (inst->opcode) {
399 assert(!"should not get here: invalid VS texture opcode");
403 switch (inst->opcode) {
428 assert(!"should not get here: invalid VS texture opcode");
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_emit.cpp | 264 brw_math_function(inst->opcode),
292 brw_math_function(inst->opcode),
308 brw_math_function(inst->opcode),
327 brw_math_function(inst->opcode),
347 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
359 brw_math_function(inst->opcode),
374 switch (inst->opcode) {
399 assert(!"should not get here: invalid VS texture opcode");
403 switch (inst->opcode) {
428 assert(!"should not get here: invalid VS texture opcode");
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrFormats.td | 60 bits<5> Opcode = 0;
62 // Top 5 bits are the 'opcode' field
63 let Inst{15-11} = Opcode;
100 // Format I instruction class in Mips : <|opcode|imm11|>
109 let Opcode = op;
115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
125 let Opcode = op;
132 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
143 let Opcode = 0b11101;
158 let Opcode = 0b11101
[all...] |
| /external/v8/src/ |
| frames.cc | 840 Translation::Opcode opcode = static_cast<Translation::Opcode>(it.Next()); local
841 ASSERT(opcode == Translation::BEGIN);
850 opcode = static_cast<Translation::Opcode>(it.Next());
851 if (opcode == Translation::JS_FRAME) {
862 opcode = static_cast<Translation::Opcode>(it.Next());
863 ASSERT(opcode == Translation::STACK_SLOT |
949 Translation::Opcode opcode = static_cast<Translation::Opcode>(it.Next()); local
967 Translation::Opcode opcode = static_cast<Translation::Opcode>(it.Next()); local
[all...] |
| /dalvik/vm/analysis/ |
| Optimize.cpp | 41 static void rewriteInstField(Method* method, u2* insns, Opcode quickOpc,
42 Opcode volatileOpc);
43 static void rewriteStaticField(Method* method, u2* insns, Opcode volatileOpc);
44 static void rewriteVirtualInvoke(Method* method, u2* insns, Opcode newOpc);
164 Opcode opc, quickOpc, volatileOpc;
372 * Update an instruction's opcode.
374 * If "opcode" is an 8-bit op, we just replace that portion. If it's a
375 * 16-bit op, we convert the opcode from "packed" form (e.g. 0x0108) to
378 static inline void updateOpcode(const Method* meth, u2* ptr, u2 opcode)
380 if (opcode >= 256)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/glx/ |
| glxcmds.c | 388 CARD8 opcode = __glXSetupForCommand(dpy); local
393 req->reqType = opcode;
529 CARD8 opcode; local
531 opcode = __glXSetupForCommand(dpy);
532 if (!opcode) {
556 req->reqType = opcode;
583 CARD8 opcode; local
585 opcode = __glXSetupForCommand(dpy);
586 if (!opcode) {
612 req->reqType = opcode;
1423 CARD8 opcode; local
1742 CARD8 opcode; local
1947 CARD8 opcode; local
2363 CARD8 opcode; local
[all...] |
| /external/mesa3d/src/glx/ |
| glxcmds.c | 388 CARD8 opcode = __glXSetupForCommand(dpy); local
393 req->reqType = opcode;
529 CARD8 opcode; local
531 opcode = __glXSetupForCommand(dpy);
532 if (!opcode) {
556 req->reqType = opcode;
583 CARD8 opcode; local
585 opcode = __glXSetupForCommand(dpy);
586 if (!opcode) {
612 req->reqType = opcode;
1423 CARD8 opcode; local
1742 CARD8 opcode; local
1947 CARD8 opcode; local
2363 CARD8 opcode; local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_optimize.c | 61 ASSERT(arg < _mesa_num_inst_src_regs(inst->Opcode));
68 switch (inst->Opcode) {
138 ASSERT(mov->Opcode == OPCODE_MOV);
225 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
269 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
324 const GLuint numDst = _mesa_num_inst_dst_regs(inst->Opcode);
392 switch (inst->Opcode) {
409 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
418 if (_mesa_num_inst_dst_regs(inst->Opcode) == 1 &&
433 * Is the given instruction opcode a flow-control opcode
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_optimize.c | 61 ASSERT(arg < _mesa_num_inst_src_regs(inst->Opcode));
68 switch (inst->Opcode) {
138 ASSERT(mov->Opcode == OPCODE_MOV);
225 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
269 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
324 const GLuint numDst = _mesa_num_inst_dst_regs(inst->Opcode);
392 switch (inst->Opcode) {
409 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
418 if (_mesa_num_inst_dst_regs(inst->Opcode) == 1 &&
433 * Is the given instruction opcode a flow-control opcode
[all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/dbgfmts/dwarf2/ |
| dwarf2-line.c | 117 dwarf_line_number_op opcode; member in struct:dwarf2_line_op
120 /* extended opcode */
244 /* Create and add a new line opcode to a section, updating offset on insertion;
248 dwarf2_dbgfmt_append_line_op(yasm_section *sect, dwarf_line_number_op opcode,
254 line_op->opcode = opcode;
265 opcode == DW_LNS_advance_line);
271 /* Create and add a new extended line opcode to a section, updating offset on
283 line_op->opcode = DW_LNS_extended_op;
307 line_op->opcode = DW_LNS_extended_op
468 unsigned int opcode; local
[all...] |
| /external/clang/lib/Sema/ |
| SemaPseudoObject.cpp | 221 BinaryOperatorKind opcode,
224 UnaryOperatorKind opcode,
273 BinaryOperatorKind opcode,
276 UnaryOperatorKind opcode,
312 BinaryOperatorKind opcode,
400 BinaryOperatorKind opcode,
402 assert(BinaryOperator::isAssignmentOp(opcode));
410 if (opcode == BO_Assign) {
413 opcode, capturedRHS->getType(),
422 BinaryOperator::getOpForCompoundAssignment(opcode);
[all...] |
| /cts/tools/vm-tests-tf/src/dot/junit/verify/b17/ |
| Test_b17.java | 25 * Having throw, return and backward goto as a last opcode in the method is tested
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| VariableSizeInsn.java | 40 public final DalvInsn withOpcode(Dop opcode) {
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| VariableSizeInsn.java | 40 public final DalvInsn withOpcode(Dop opcode) {
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| NormalSsaInsn.java | 130 * @return the Rop opcode for this insn
223 Rop opcode = getOpcode(); local
225 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
232 switch (opcode.getOpcode()) {
|
| /dalvik/vm/compiler/ |
| Loop.h | 30 Opcode loopBranchOpcode; // OP_IF_XXX for the loop back branch
|
| /dalvik/vm/compiler/template/armv5te/ |
| TemplateOpList.h | 18 * Dalvik opcode list that uses additional templates to complete JIT execution.
|
