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  /external/llvm/lib/Target/R600/
SIISelLowering.cpp 696 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
815 unsigned RegClass = Desc->OpInfo[Op].RegClass;
852 unsigned RegClass = Desc->OpInfo[Op].RegClass;
864 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
886 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
    [all...]
R600InstrInfo.cpp 689 switch (MI->getDesc().OpInfo->RegClass) {
    [all...]
  /external/llvm/lib/Transforms/Scalar/
CodeGenPrepare.cpp     [all...]
  /external/llvm/lib/CodeGen/
TargetSchedule.cpp 213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
MachineInstr.cpp     [all...]
MachineVerifier.cpp 815 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
823 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
    [all...]
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCTargetDesc.cpp 252 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
  /external/llvm/utils/TableGen/
AsmWriterEmitter.cpp 418 O<<" static const uint32_t OpInfo[] = {\n";
428 // Add a second OpInfo table only when it is necessary.
453 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n"
458 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n";
    [all...]
CodeGenDAGPatterns.cpp     [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
SIInstrInfo.td 54 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
56 let MIOperandInfo = opInfo;
R600InstrInfo.cpp 253 switch (MI->getDesc().OpInfo->RegClass) {
  /external/mesa3d/src/gallium/drivers/radeon/
SIInstrInfo.td 54 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
56 let MIOperandInfo = opInfo;
R600InstrInfo.cpp 253 switch (MI->getDesc().OpInfo->RegClass) {
  /external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 464 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
465 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY)
466 || (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
    [all...]
  /external/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 559 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
564 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
565 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
624 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
629 if (OpInfo[i].isPredicate()) {
661 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 221 if (II.OpInfo[i].isOptionalDef()) {
310 MCID.OpInfo[IIOpNum].isOptionalDef();
    [all...]
  /dalvik/dx/src/com/android/dx/cf/code/
ByteOps.java 647 public static int opInfo(int opcode) {
BytecodeArray.java 224 int info = ByteOps.opInfo(opcode);
    [all...]
  /external/llvm/include/llvm/Target/
TargetLowering.h     [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/
nv50_ir_emit_nv50.cpp     [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/
nv50_ir_emit_nvc0.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 841 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
    [all...]
  /external/mesa3d/src/gallium/drivers/nv50/codegen/
nv50_ir_emit_nv50.cpp     [all...]
  /external/mesa3d/src/gallium/drivers/nvc0/codegen/
nv50_ir_emit_nvc0.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 261 if (MCID.OpInfo[i].isPredicate())
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12 3