HomeSort by relevance Sort by last modified time
    Searched full:reg2 (Results 51 - 75 of 262) sorted by null

1 23 4 5 6 7 8 91011

  /dalvik/vm/compiler/codegen/x86/
LowerHelper.cpp 322 int reg, int reg2, LowOpndRegType type) {
325 reg-reg2, size==OpndSize_64, stream);
328 stream = encoder_reg_reg(m, size, reg, true, reg2, true, type, stream);
338 int reg2, bool isPhysical2, LowOpndRegType type) {
339 return lower_reg_reg(m, ATOM_NORMAL, size, reg, reg2, type);
352 int reg2, bool isPhysical2, LowOpndRegType type) {
356 if(isMnemonicMove(m) && regAll == reg2) return NULL;
357 return lower_reg_reg(m, ATOM_NORMAL, size, regAll, reg2, type);
359 stream = encoder_reg_reg(m, size, reg, isPhysical, reg2, isPhysical2, type, stream);
368 int reg2, bool isPhysical2, LowOpndRegType type)
    [all...]
Lower.h 646 int reg2, bool isPhysical2);
648 int reg2, bool isPhysical2);
652 int reg2, bool isPhysical2);
656 int reg2, bool isPhysical2);
701 int reg2, bool isPhysical2);
708 int reg2, bool isPhysical2);
710 int reg2, bool isPhysical2);
727 int reg2, bool isPhysical2);
741 int reg2, bool isPhysical2);
744 int reg2, bool isPhysical2)
    [all...]
  /external/pixman/pixman/
pixman-arm-neon-asm.h 84 .macro pixldst2 op, elem_size, reg1, reg2, mem_operand, abits variable
86 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&, :&abits&]!
88 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&]!
92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits variable
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]! variable
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]! variable
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand variable
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]! variable
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand variable
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&] variable
256 .macro pixld2_s elem_size, reg1, reg2, mem_operand variable
276 pixld1_s elem_size, reg2, mem_operand variable
    [all...]
pixman-arm-neon-asm-bilinear.S 91 .macro bilinear_load_8888 reg1, reg2, tmp
96 vld1.32 {reg2}, [TMP1]
99 .macro bilinear_load_0565 reg1, reg2, tmp
103 vld1.32 {reg2[0]}, [TMP1], STRIDE
104 vld1.32 {reg2[1]}, [TMP1]
105 convert_four_0565_to_x888_packed reg2, reg1, reg2, tmp
109 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
111 bilinear_load_8888 reg1, reg2, tmp1
113 vmlal.u8 acc1, reg2, d2
    [all...]
  /art/compiler/dex/quick/arm/
codegen_arm.h 49 bool SameRegType(int reg1, int reg2);
66 void FlushRegWide(int reg1, int reg2);
159 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
  /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/
x86masm.pl 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
56 if ($reg2 ne "")
58 $ret .= "$reg2*$idx";
  /external/openssl/crypto/perlasm/
x86masm.pl 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
56 if ($reg2 ne "")
58 $ret .= "$reg2*$idx";
  /external/llvm/test/CodeGen/ARM/
vext.ll 173 ;CHECK: vmov.16 [[REG2:d[0-9]+]][0]
174 ;CHECK: vmov.16 [[REG2]][1]
175 ;CHECK: vmov.16 [[REG2]][2]
176 ;CHECK: vmov.16 [[REG2]][3]
avoid-cpsr-rmw.ll 11 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
12 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
memcpy-inline.ll 41 ; CHECK: ldr [[REG2:r[0-9]+]], [r1, #32]
42 ; CHECK: str [[REG2]], [r0, #32]
  /external/v8/src/
regexp-macro-assembler-tracer.cc 300 int reg2,
302 PrintF(" CheckNotRegistersEqual(reg1=%d, reg2=%d, label[%08x]);\n",
304 reg2,
306 assembler_->CheckNotRegistersEqual(reg1, reg2, on_not_equal);
regexp-macro-assembler-tracer.h 62 virtual void CheckNotRegistersEqual(int reg1, int reg2, Label* on_not_equal);
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sound/
sb.h 335 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
336 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
357 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
360 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
  /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sound/
sb.h 335 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
336 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
357 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
360 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
  /external/llvm/test/CodeGen/SystemZ/
loop-01.ll 93 ; CHECK: lr [[REG2:%r[0-5]]], [[REG]]
94 ; CHECK: stg [[REG2]],
  /dalvik/vm/compiler/codegen/x86/libenc/
enc_wrapper.cpp 226 int reg2, bool isPhysical2, LowOpndRegType type, char * stream) {
227 if((m == Mnemonic_MOV || m == Mnemonic_MOVQ) && reg == reg2) return stream;
229 add_r(args, reg2, size); //destination
476 int reg, bool isPhysical, int reg2,
479 add_r(args, reg2, OpndSize_32); //destination
490 int reg, bool isPhysical,int reg2,
493 add_r(args, reg2, OpndSize_32); //destination
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_fragshader.c 49 GLuint reg2 = 0; local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT;
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT;
109 SET_INST_2(opnum, optype) |= reg2;
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c 49 GLuint reg2 = 0; local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT;
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT;
109 SET_INST_2(opnum, optype) |= reg2;
  /dalvik/vm/compiler/codegen/mips/
CodegenFactory.cpp 284 int reg1, int reg2, int dOffset,
290 res = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
295 res = newLIR3(cUnit, kMipsSltu, tReg, reg1, reg2);
  /external/valgrind/main/none/tests/s390x/
cksm.c 26 register uint64_t reg2 asm("2") = (uint64_t) buff;
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
37 addr = reg2;
  /art/compiler/dex/quick/mips/
target_mips.cc 95 bool MipsMir2Lir::SameRegType(int reg1, int reg2) {
96 return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
312 void MipsMir2Lir::FlushRegWide(int reg1, int reg2) {
314 RegisterInfo* info2 = GetRegInfo(reg2);
  /art/compiler/dex/quick/x86/
target_x86.cc 104 bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
105 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
316 void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
318 RegisterInfo* info2 = GetRegInfo(reg2);
  /external/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.h 101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 116 unsigned Reg2, bool isKill2) {
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
  /external/llvm/test/CodeGen/PowerPC/
stack-realign.ll 93 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
97 ; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]

Completed in 319 milliseconds

1 23 4 5 6 7 8 91011