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  /external/llvm/lib/Target/Mips/
Mips16InstrInfo.cpp 266 unsigned Reg1, unsigned Reg2) const {
270 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
273 // move reg2, sp
274 // add reg1, reg1, reg2
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
284 MIB3.addReg(Reg2, RegState::Kill);
Mips16InstrInfo.h 120 unsigned Reg1, unsigned Reg2) const;
  /art/compiler/dex/quick/mips/
int_mips.cc 226 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2,
228 NewLIR4(kMipsDiv, r_HI, r_LO, reg1, reg2);
253 void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
  /external/llvm/test/CodeGen/ARM/
vector-DAGCombine.ll 207 ; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]]
209 ; CHECK: vld1.32 {[[REG2]][0]}, [r2]
210 ; CHECK: vmull.u8 q{{[0-9]+}}, [[REG1]], [[REG2]]
  /external/chromium_org/v8/src/mips/
macro-assembler-mips.cc 485 Register reg2) {
506 // reg2 - Used for the index into the dictionary.
519 // Use reg2 for index calculations and keep the hash intact in reg0.
520 mov(reg2, reg0);
523 Addu(reg2, reg2, Operand(SeededNumberDictionary::GetProbeOffset(i)));
525 and_(reg2, reg2, reg1);
529 sll(at, reg2, 1); // 2x.
530 addu(reg2, reg2, at); // reg2 = reg2 * 3
    [all...]
  /external/v8/src/
regexp-macro-assembler-irregexp.cc 375 int reg2,
380 Emit32(reg2);
regexp-macro-assembler-irregexp.h 99 virtual void CheckNotRegistersEqual(int reg1, int reg2, Label* on_not_equal);
  /external/v8/src/mips/
macro-assembler-mips.cc 464 Register reg2) {
485 // reg2 - Used for the index into the dictionary.
499 // Use reg2 for index calculations and keep the hash intact in reg0.
500 mov(reg2, reg0);
503 Addu(reg2, reg2, Operand(SeededNumberDictionary::GetProbeOffset(i)));
505 and_(reg2, reg2, reg1);
509 sll(at, reg2, 1); // 2x.
510 addu(reg2, reg2, at); // reg2 = reg2 * 3
    [all...]
  /art/compiler/dex/quick/arm/
target_arm.cc 94 bool ArmMir2Lir::SameRegType(int reg1, int reg2) {
95 return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2));
612 void ArmMir2Lir::FlushRegWide(int reg1, int reg2) {
614 RegisterInfo* info2 = GetRegInfo(reg2);
  /art/compiler/dex/quick/
mir_to_lir.h 390 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2,
548 virtual bool SameRegType(int reg1, int reg2) = 0;
565 virtual void FlushRegWide(int reg1, int reg2) = 0;
    [all...]
  /dalvik/vm/compiler/codegen/
Ralloc.h 202 extern void dvmCompilerFlushRegWide(CompilationUnit *cUnit, int reg1, int reg2);
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 137 unsigned Reg2 = MI->getOperand(Idx2).getReg();
148 Reg0 = Reg2;
150 } else if (HasDef && Reg0 == Reg2 &&
168 MI->getOperand(Idx1).setReg(Reg2);
  /external/pixman/pixman/
pixman.h 455 pixman_region16_t *reg2);
458 pixman_region16_t *reg2);
550 pixman_region32_t *reg2);
553 pixman_region32_t *reg2);
    [all...]
pixman-arm-simd-asm.h 99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0 variable
104 op&r&cond WK&reg2, [base], #4 variable
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3} variable
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base variable
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3} variable
pixman-arm-neon-asm.S     [all...]
  /external/skia/gm/
bitmaprect.cpp 248 static skiagm::GMRegistry reg2(MyFactory2);
complexclip2.cpp 172 static GMRegistry reg2(MyFactory2);
  /external/aac/libFDK/src/
fixpoint_math.cpp 430 FIXP_DBL reg1, reg2, regtmp ; local
446 reg2 = FL2FXCONST_DBL(0.0625f); /* 0.5 >> 3 */
449 regtmp= reg2 - fMultDiv2(regtmp, val); /* b = 0.5 - 2 * V * Q^2 */
454 reg2 = FL2FXCONST_DBL(0.707106781186547524400844362104849f); /* 1/sqrt(2); */
455 reg1 = fMultDiv2(reg1, reg2) << 2;
  /art/compiler/dex/quick/x86/
assemble_x86.cc     [all...]
  /external/chromium_org/v8/src/arm/
macro-assembler-arm.cc 209 Register reg2,
213 eor(reg1, reg1, Operand(reg2), LeaveCC, cond);
214 eor(reg2, reg2, Operand(reg1), LeaveCC, cond);
215 eor(reg1, reg1, Operand(reg2), LeaveCC, cond);
218 mov(reg1, reg2, LeaveCC, cond);
219 mov(reg2, scratch, LeaveCC, cond);
    [all...]
  /dalvik/vm/compiler/codegen/x86/
CodegenInterface.cpp 525 mov imm32, reg2
526 call reg2
531 mov imm32, reg2
532 call reg2
537 mov imm32, reg2
538 call reg2
    [all...]
  /dalvik/vm/compiler/codegen/mips/FP/
MipsFP.cpp 23 int reg1, int reg2);
  /dalvik/vm/compiler/codegen/mips/
RallocUtil.cpp 107 static void flushRegWide(CompilationUnit *cUnit, int reg1, int reg2)
110 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
1017 int reg1, int reg2)
1019 flushRegWide(cUnit, reg1, reg2);
    [all...]
  /external/v8/src/ia32/
regexp-macro-assembler-ia32.h 72 virtual void CheckNotRegistersEqual(int reg1, int reg2, Label* on_not_equal);
  /external/grub/netboot/
eepro.c 227 #define REG2 0x02
314 temp_reg = inb(ioaddr + REG2); /* match broadcast */
315 outb(temp_reg | 0x14, ioaddr + REG2);

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