| /external/llvm/test/CodeGen/NVPTX/ |
| arithmetic-int.ll | 35 %ret = sdiv i64 %a, %b
132 %ret = sdiv i32 %a, %b
225 %ret = sdiv i16 %a, %b
|
| /external/llvm/include/llvm/ADT/ |
| APSInt.h | 102 *this = sdiv(RHS);
111 return IsUnsigned ? APSInt(udiv(RHS), true) : APSInt(sdiv(RHS), false);
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 232 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
234 bool UseSignedOp = Opcode == Instruction::SDiv ||
|
| /external/llvm/test/CodeGen/ARM/ |
| 2010-06-21-LdStMultipleBug.ll | 44 %iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2]
50 %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3]
|
| 2007-05-14-RegScavengerAssert.ll | 22 %tmp68 = sdiv i64 0, 0 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| 2008-04-28-CoalescerBug.ll | 99 %tmp13337 = sdiv i64 0, 0 ; <i64> [#uses=1]
112 %tmp13358 = sdiv i64 %tmp13354, %tmp13357 ; <i64> [#uses=1]
|
| 2007-11-30-LoadFolding-Bug.ll | 24 %tmp22.i = sdiv i32 0, 2 ; <i32> [#uses=2]
|
| atom-call-reg-indirect-foldedreload64.ll | 63 %div = sdiv i32 %7, %8
|
| early-ifcvt.ll | 154 %3 = sdiv i32 %a, %b
|
| /external/llvm/test/Transforms/LICM/ |
| sinking.ll | 223 %tmp.6 = sdiv i32 %N, %N_addr.0.pn ; <i32> [#uses=1]
232 ; CHECK-NEXT: %tmp.6 = sdiv i32 %N, %N_addr.0.pn
|
| /external/llvm/include/llvm/IR/ |
| Instruction.def | 115 HANDLE_BINARY_INST(15, SDiv , BinaryOperator)
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64instrs.ll | 93 %div = sdiv i64 %a, %b
|
| /external/llvm/test/CodeGen/PowerPC/ |
| ctrloop-i64.ll | 37 %conv = sdiv i64 %x.05, %d
|
| /external/llvm/test/CodeGen/R600/ |
| schedule-fs-loop-nested.ll | 11 %5 = sdiv i32 %4, 4
|
| /external/llvm/test/Transforms/Inline/ |
| 2009-01-13-RecursiveInlineCrash.ll | 151 %5 = sdiv i32 %size, 2 ; <i32> [#uses=1]
155 %9 = sdiv i32 %size, 2 ; <i32> [#uses=1]
160 %14 = sdiv i32 %size, 2 ; <i32> [#uses=1]
165 %19 = sdiv i32 %size, 2 ; <i32> [#uses=1]
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| 2012-01-02-nopreheader.ll | 21 %0 = sdiv i32 %n, undef
|
| /external/llvm/unittests/ADT/ |
| APIntTest.cpp | 168 EXPECT_EQ(neg_one, one.sdiv(neg_one));
169 EXPECT_EQ(neg_one, neg_one.sdiv(one));
170 EXPECT_EQ(one, neg_one.sdiv(neg_one));
171 EXPECT_EQ(one, one.sdiv(one));
|
| /external/llvm/utils/vim/ |
| llvm.vim | 32 syn keyword llvmStatement ret sdiv select sext sge sgt shl shufflevector sitofp
|
| /external/llvm/test/Other/ |
| lint.ll | 37 %sd = sdiv i32 2, 0
|
| /external/llvm/utils/kate/ |
| llvm.xml | 128 <item> sdiv </item>
|
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 436 inline BinaryOp_match<LHS, RHS, Instruction::SDiv>
438 return BinaryOp_match<LHS, RHS, Instruction::SDiv>(L, R);
539 /// m_IDiv - Matches UDiv and SDiv.
541 inline BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>
543 return BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>(L, R);
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 426 /// Keyword sdiv, float, ...
646 INSTKEYWORD(udiv, UDiv); INSTKEYWORD(sdiv, SDiv); INSTKEYWORD(fdiv, FDiv);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
196 case ISD::SDIV:
|
| /external/clang/test/CodeGen/ |
| vla.c | 141 // CHECK-NEXT: [[T7:%.*]] = sdiv exact i32 [[T4]], [[T6]]
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 130 case Instruction::SDiv:
|
