| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 321 case ISD::SETGT:
|
| R600Instructions.td | 679 0x09, "SETGT",
773 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfoV4.td | [all...] |
| HexagonISelDAGToDAG.cpp | [all...] |
| HexagonInstrInfo.td | 497 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
559 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
618 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
633 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600Instructions.td | 279 0x09, "SETGT",
417 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600Instructions.td | 279 0x09, "SETGT",
417 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | 258 case ISD::SETGT:
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 452 case ISD::SETGT:
|
| MipsISelLowering.cpp | 465 case ISD::SETGT:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrNEON.td | 560 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| cast.ll | 121 ; %X = setlt sbyte %c, 0 ; setgt %A, 127
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 762 case ISD::SETGT:
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | [all...] |
| NVPTXInstrInfo.td | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
