| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 623 unsigned VReg = MRI.createVirtualRegister(RC);
624 MRI.addLiveIn(VA.getLocReg(), VReg);
625 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
674 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
676 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
[all...] |
| /art/runtime/ |
| thread.cc | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
854 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
[all...] |
| MachineScheduler.cpp | [all...] |
| LiveDebugVariables.cpp | 566 // Collect all the (vreg, valno) pairs that are copies of LI.
[all...] |
| PrologEpilogInserter.cpp | [all...] |
| InlineSpiller.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 218 /// consecutive vreg numbers and return the first assigned number.
|
| ScheduleDAGRRList.cpp | [all...] |
| SelectionDAGISel.cpp | 416 // If Reg is live-in then update debug info to track its copy in a vreg.
433 // If this vreg is directly copied into an exported register then
555 // If this is a CopyToReg with a vreg dest, process it.
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 532 /// maintain the number of vreg uses remaining to be top-scheduled.
|
| /external/valgrind/main/VEX/priv/ |
| host_x86_defs.h | 727 HReg vreg, Short spill_off );
|
| /art/compiler/dex/ |
| mir_optimization.cc | 363 // Almost there. Are the instructions targeting the same vreg?
[all...] |
| /art/compiler/dex/quick/arm/ |
| int_arm.cc | 188 LOG(INFO) << "vreg = " << mir_graph_->SRegToVReg(dest_sreg);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 281 bool isVRegCycle : 1; // May use and def the same vreg.
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /prebuilts/gcc/darwin-x86/x86/i686-linux-android-4.7/lib/gcc/i686-linux-android/4.7/include/ |
| avx2intrin.h | 161 /* In that case (__N*8) will be in vreg, and insn will not be matched. */
[all...] |
| /prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/lib/gcc/i686-linux-android/4.7/include/ |
| avx2intrin.h | 161 /* In that case (__N*8) will be in vreg, and insn will not be matched. */
[all...] |
| /external/chromium_org/v8/src/arm/ |
| lithium-arm.cc | 668 int vreg = allocator_->GetVirtualRegister(); local
671 vreg = 0;
673 operand->set_virtual_register(vreg);
[all...] |
| /external/chromium_org/v8/src/ia32/ |
| lithium-ia32.cc | 733 int vreg = allocator_->GetVirtualRegister(); local
736 vreg = 0;
738 operand->set_virtual_register(vreg);
[all...] |
| /external/chromium_org/v8/src/mips/ |
| lithium-mips.cc | 673 int vreg = allocator_->GetVirtualRegister(); local
676 vreg = 0;
678 operand->set_virtual_register(vreg);
[all...] |
| /external/chromium_org/v8/src/x64/ |
| lithium-x64.cc | 677 int vreg = allocator_->GetVirtualRegister(); local
680 vreg = 0;
682 operand->set_virtual_register(vreg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 767 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
768 MF.getRegInfo().addLiveIn(PReg, VReg);
769 return VReg;
[all...] |
| /external/llvm/docs/ |
| CodeGenerator.rst | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 66 /// \brief The specified machine instr operand is a vreg, and that
67 /// vreg is being provided by the specified load instruction. If possible,
[all...] |
