| /dalvik/vm/compiler/codegen/mips/ |
| CodegenDriver.cpp | 131 switch (mir->dalvikInsn.opcode) {
188 switch (mir->dalvikInsn.opcode) {
242 Opcode opcode = mir->dalvikInsn.opcode; local
244 switch (opcode) {
272 static void selfVerificationBranchInsert(LIR *currentLIR, Mipsopcode opcode,
277 insn->opcode = opcode;
313 Templateopcode opcode = TEMPLATE_MEM_OP_DECODE local
944 Opcode opcode = mir->dalvikInsn.opcode; local
1722 Opcode opcode = mir->dalvikInsn.opcode; local
1786 Opcode opcode = mir->dalvikInsn.opcode; local
2031 Opcode opcode = mir->dalvikInsn.opcode; local
2733 Opcode opcode = mir->dalvikInsn.opcode; local
2758 Opcode opcode = mir->dalvikInsn.opcode; local
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/io/ |
| Opcodes.java | 20 * All the Dalvik opcode value constants. See the related spec
21 * document for the meaning and instruction format of each opcode.
25 * pseudo-opcode used for nonstandard format payload "instructions". TODO:
32 * pseudo-opcode used to indicate there is no next opcode; used
33 * in opcode chaining lists
37 /** minimum valid opcode value */
40 /** maximum valid opcode value */
43 // BEGIN(opcodes); GENERATED AUTOMATICALLY BY opcode-gen
303 // TODO: Generate these payload opcodes with opcode-gen
[all...] |
| /external/qemu/hw/ |
| goldfish_mmc.c | 166 struct mmc_opcode* opcode = mmc_opcodes;
168 while (opcode->cmd != command && opcode->cmd != -1) opcode++;
169 return opcode->name;
219 int opcode = cmd & 63; local
221 // fprintf(stderr, "goldfish_mmc_do_command opcode: %s (0x%04X), arg: %d\n", get_command_name(opcode), cmd, arg);
230 switch (opcode) {
|
| /dalvik/dx/src/com/android/dx/cf/code/ |
| RopperMachine.java | 164 * Gets the return opcode encountered, if any.
166 * @return {@code null-ok;} the return opcode
280 public void run(Frame frame, int offset, int opcode) {
282 * This is the stack pointer after the opcode's arguments have been
288 RegisterSpecList sources = getSources(opcode, stackPointer);
291 super.run(frame, offset, opcode);
294 RegisterSpec localTarget = getLocalTarget(opcode == ByteOps.ISTORE);
300 switch (opcode) {
361 if (opcode == ByteOps.MULTIANEWARRAY) {
459 opcode = ByteOps.CHECKCAST
[all...] |
| ValueAwareMachine.java | 41 public void run(Frame frame, int offset, int opcode) {
42 switch (opcode) {
193 Hex.u1(opcode));
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 42 c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
119 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
122 for (i = 0; i < opcode->NumSrcRegs; ++i) {
127 if (opcode->HasDstReg) {
145 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
148 for(i = 0; i < opcode->NumSrcRegs; ++i) {
177 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
200 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
300 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
344 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| r3xx_vertprog.c | 375 const struct rc_opcode_info *info = rc_get_opcode_info(vpi->Opcode);
395 (vpi->Opcode != RC_OPCODE_SEQ &&
396 vpi->Opcode != RC_OPCODE_SNE));
398 switch (vpi->Opcode) {
511 rc_error(&compiler->Base, "Unknown opcode %s\n", info->Name);
568 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
570 for (i = 0; i < opcode->NumSrcRegs; ++i) {
577 if (opcode->HasDstReg) {
591 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode) local
626 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
667 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); local
706 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
812 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
827 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| r300_fragprog_emit.c | 105 static unsigned int translate_rgb_opcode(struct r300_fragment_program_compiler * c, rc_opcode opcode)
107 switch(opcode) {
114 error("translate_rgb_opcode: Unknown opcode %s", rc_get_opcode_info(opcode)->Name);
125 static unsigned int translate_alpha_opcode(struct r300_fragment_program_compiler * c, rc_opcode opcode)
127 switch(opcode) {
136 error("translate_rgb_opcode: Unknown opcode %s", rc_get_opcode_info(opcode)->Name);
164 code->alu.inst[ip].rgb_inst = translate_rgb_opcode(c, inst->RGB.Opcode);
165 code->alu.inst[ip].alpha_inst = translate_alpha_opcode(c, inst->Alpha.Opcode);
427 unsigned int opcode; local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 42 c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
119 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
122 for (i = 0; i < opcode->NumSrcRegs; ++i) {
127 if (opcode->HasDstReg) {
145 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
148 for(i = 0; i < opcode->NumSrcRegs; ++i) {
177 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
200 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
300 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
344 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| r3xx_vertprog.c | 375 const struct rc_opcode_info *info = rc_get_opcode_info(vpi->Opcode);
395 (vpi->Opcode != RC_OPCODE_SEQ &&
396 vpi->Opcode != RC_OPCODE_SNE));
398 switch (vpi->Opcode) {
511 rc_error(&compiler->Base, "Unknown opcode %s\n", info->Name);
568 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
570 for (i = 0; i < opcode->NumSrcRegs; ++i) {
577 if (opcode->HasDstReg) {
591 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode) local
626 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
667 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode); local
706 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
812 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
827 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 77 const char* GetTargetInstFmt(int opcode);
78 const char* GetTargetInstName(int opcode);
81 uint64_t GetTargetInstFlags(int opcode);
86 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
94 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
99 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
101 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
103 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
|
| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 78 const char* GetTargetInstFmt(int opcode);
79 const char* GetTargetInstName(int opcode);
82 uint64_t GetTargetInstFlags(int opcode);
87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
95 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
100 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
102 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
104 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
106 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
|
| fp_x86.cc | 23 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode,
32 switch (opcode) {
61 LOG(FATAL) << "Unexpected opcode: " << opcode;
78 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode,
83 switch (opcode) {
112 LOG(FATAL) << "Unexpected opcode: " << opcode;
133 void X86Mir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest,
139 switch (opcode) {
[all...] |
| /external/javassist/src/main/javassist/bytecode/analysis/ |
| Analyzer.java | 31 import javassist.bytecode.Opcode;
85 public class Analyzer implements Opcode {
182 int opcode = iter.byteAt(pos); local
184 if (opcode == TABLESWITCH) {
186 } else if (opcode == LOOKUPSWITCH) {
188 } else if (opcode == RET) {
190 } else if (Util.isJumpInstruction(opcode)) {
193 if (Util.isJsr(opcode)) {
196 } else if (! Util.isGoto(opcode)) {
201 } else if (opcode != ATHROW && ! Util.isReturn(opcode))
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| MethodInliner.java | 252 byte opcode;
260 opcode = InstructionConstants.OP_ISTORE;
264 opcode = InstructionConstants.OP_LSTORE;
268 opcode = InstructionConstants.OP_FSTORE;
272 opcode = InstructionConstants.OP_DSTORE;
276 opcode = InstructionConstants.OP_ASTORE;
281 new VariableInstruction(opcode, variableOffset + parameterOffset + parameterIndex).shrink());
332 switch (simpleInstruction.opcode)
382 switch (constantInstruction.opcode)
|
| /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/ |
| x86masm.pl | 14 { my ($opcode,@arg)=@_;
19 if ($opcode =~ /lea/ && @arg[1] =~ s/.*PTR\s+(\(.*\))$/OFFSET $1/) # no []
20 { $opcode="mov"; }
21 elsif ($opcode !~ /movq/)
27 &::emit($opcode,@arg);
|
| /external/openssl/crypto/perlasm/ |
| x86masm.pl | 14 { my ($opcode,@arg)=@_;
19 if ($opcode =~ /lea/ && @arg[1] =~ s/.*PTR\s+(\(.*\))$/OFFSET $1/) # no []
20 { $opcode="mov"; }
21 elsif ($opcode !~ /movq/)
27 &::emit($opcode,@arg);
|
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Analysis/ |
| OdexedFieldInstructionMapper.java | 31 import org.jf.dexlib.Code.Opcode;
34 private static Opcode[][][][] opcodeMap = new Opcode[][][][] {
36 new Opcode[][][] {
38 new Opcode[][] {
40 new Opcode[] {
41 /*Z*/ Opcode.IGET_QUICK,
42 /*B*/ Opcode.IGET_QUICK,
43 /*S*/ Opcode.IGET_QUICK,
44 /*C*/ Opcode.IGET_QUICK
[all...] |
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/ |
| pickletools.py | 7 Generate all the opcodes in a pickle, as (opcode, arg, position) triples.
37 executed once each, from first to last, until a STOP opcode is reached.
43 literal immediately following the INT opcode in the pickle bytestream. Other
45 whatever object is left on the stack when the final STOP opcode is executed.
81 unpickling). "Opcode bloat" isn't so much a subtlety as a source of
87 For compatibility, the meaning of a pickle opcode never changes. Instead new
96 the older unpickler) opcode.
109 int as 4 bytes following the opcode, which is cheaper to unpickle than the
150 # Some pickle opcodes have an argument, following the opcode in the
154 # the opcode stream, immediately following an opcode
[all...] |
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/ |
| pickletools.py | 7 Generate all the opcodes in a pickle, as (opcode, arg, position) triples.
37 executed once each, from first to last, until a STOP opcode is reached.
43 literal immediately following the INT opcode in the pickle bytestream. Other
45 whatever object is left on the stack when the final STOP opcode is executed.
81 unpickling). "Opcode bloat" isn't so much a subtlety as a source of
87 For compatibility, the meaning of a pickle opcode never changes. Instead new
96 the older unpickler) opcode.
109 int as 4 bytes following the opcode, which is cheaper to unpickle than the
150 # Some pickle opcodes have an argument, following the opcode in the
154 # the opcode stream, immediately following an opcode
[all...] |
| /art/compiler/dex/ |
| vreg_analysis.cc | 86 int attrs = oat_data_flow_attributes_[mir->dalvikInsn.opcode];
160 if ((mir->dalvikInsn.opcode == Instruction::RETURN) ||
161 (mir->dalvikInsn.opcode == Instruction::RETURN_WIDE) ||
162 (mir->dalvikInsn.opcode == Instruction::RETURN_OBJECT)) {
192 Instruction::Code opcode = mir->dalvikInsn.opcode; local
193 int flags = (static_cast<int>(opcode) >= kNumPackedOpcodes)
194 ? 0 : Instruction::FlagsOf(mir->dalvikInsn.opcode);
204 if (move_result_mir && (move_result_mir->dalvikInsn.opcode !=
218 if (((mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC) &
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| NormalSsaInsn.java | 130 * @return the Rop opcode for this insn
223 Rop opcode = getOpcode(); local
225 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
232 switch (opcode.getOpcode()) {
|
| /external/chromium_org/third_party/WebKit/Source/devtools/front_end/ |
| ResourceWebSocketFrameView.js | 66 } else if (payload.opcode == WebInspector.ResourceWebSocketFrameView.OpCodes.TextFrame) {
72 rowClass = "opcode";
74 switch (payload.opcode) {
91 row.data = WebInspector.UIString("%s (Opcode %d%s)", opcodeMeaning, payload.opcode, (payload.mask ? ", mask" : ""));
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 85 bool isFCOp(unsigned opcode) const;
86 bool isTexOp(unsigned opcode) const;
397 unsigned opcode = MI.getOpcode(); local
398 bool hasOffsets = (opcode == AMDGPU::TEX_LD);
445 if (opcode == AMDGPU::TEX_SAMPLE_C_L || opcode == AMDGPU::TEX_SAMPLE_C_LB) {
475 && opcode != AMDGPU::TEX_SAMPLE_C_L
476 && opcode != AMDGPU::TEX_SAMPLE_C_LB) {
634 bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
635 switch(opcode) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_fs_cse.cpp | 48 switch (inst->opcode) {
106 if (inst->opcode == entry->generator->opcode &&
|
