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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp 237 if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) ||
238 AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) {
274 if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
295 case AMDGPU::M0: return 124;
296 case AMDGPU::SREG_LIT_0: return 128;
AMDGPUMCTargetDesc.cpp 1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
10 // This file provides AMDGPU specific target descriptions.
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp 237 if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) ||
238 AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) {
274 if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
295 case AMDGPU::M0: return 124;
296 case AMDGPU::SREG_LIT_0: return 128;
AMDGPUMCTargetDesc.cpp 1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
10 // This file provides AMDGPU specific target descriptions.
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
  /external/llvm/lib/Target/R600/
AMDGPUInstrInfo.cpp 92 case AMDGPU::BRANCH_COND_i32:
93 case AMDGPU::BRANCH_COND_f32:
94 case AMDGPU::BRANCH:
SIInstrInfo.h 78 namespace AMDGPU {
85 } // End namespace AMDGPU
R600OptimizeVectorRegisters.cpp 32 #include "AMDGPU.h"
63 assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
132 case AMDGPU::R600_ExportSwz:
133 case AMDGPU::EG_ExportSwz:
186 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
191 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
208 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
325 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) {
SIInsertWaits.cpp 19 #include "AMDGPU.h"
132 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
165 if (MI.getOpcode() == AMDGPU::EXP)
216 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
244 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
293 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUMCInstLower.cpp 1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
10 // This file contains code to lower AMDGPU MachineInstrs to their corresponding
62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
AMDILCFGStructurizer.cpp     [all...]
AMDILISelDAGToDAG.cpp 32 // AMDGPUDAGToDAGISel - AMDGPU specific code to select AMDGPU machine instructions
37 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
79 // createAMDGPUISelDag - This pass converts a legalized DAG into a AMDGPU-specific
166 unsigned int NewOpc = AMDGPU::COPY;
308 return "AMDGPU DAG->DAG Pattern Instruction Selection";
316 ///==== AMDGPU Functions ====///
372 AMDGPU::ZERO, MVT::i32);
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUMCInstLower.cpp 1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
10 // This file contains code to lower AMDGPU MachineInstrs to their corresponding
62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
AMDILCFGStructurizer.cpp     [all...]
AMDILISelDAGToDAG.cpp 32 // AMDGPUDAGToDAGISel - AMDGPU specific code to select AMDGPU machine instructions
37 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
79 // createAMDGPUISelDag - This pass converts a legalized DAG into a AMDGPU-specific
166 unsigned int NewOpc = AMDGPU::COPY;
308 return "AMDGPU DAG->DAG Pattern Instruction Selection";
316 ///==== AMDGPU Functions ====///
372 AMDGPU::ZERO, MVT::i32);
  /external/llvm/lib/Target/R600/MCTargetDesc/
AMDGPUMCTargetDesc.cpp 1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
  /external/llvm/lib/Target/R600/InstPrinter/
AMDGPUInstPrinter.cpp 1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
33 case AMDGPU::PRED_SEL_OFF: break;

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