| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| PPCISelDAGToDAG.cpp | 229 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
230 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
232 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
246 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
265 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
266 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
269 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
270 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| ARMConstantIslandPass.cpp | 545 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
[all...] |
| ARMInstrInfo.cpp | 126 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
|
| ARMLoadStoreOptimizer.cpp | 338 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
[all...] |
| MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
|
| Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 786 BuildMI(*PH, InsertPos, DL, SubD, SubR);
812 BuildMI(*PH, InsertPos, DL, AddD, AddR)
833 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
[all...] |
| HexagonNewValueJump.cpp | 610 NewMI = BuildMI(*MBB, jmpPos, dl,
621 NewMI = BuildMI(*MBB, jmpPos, dl,
627 NewMI = BuildMI(*MBB, jmpPos, dl,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86VZeroUpper.cpp | 269 BuildMI(BB, I, dl, TII->get(X86::VZEROUPPER));
|
| X86FloatingPoint.cpp | 253 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
262 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
845 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchFixupPass.cpp | 376 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
512 InvertedMI = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(InvertedOpcode));
588 BuildMI(MBB, DebugLoc(), TII->get(AArch64::Bimm))
|
| AArch64ISelLowering.cpp | 386 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
393 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
396 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
404 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
405 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
481 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
485 BuildMI(BB, dl, TII->get(CmpOp))
488 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
495 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
497 BuildMI(BB, dl, TII->get(AArch64::CBNZw)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 308 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Opc))
316 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
320 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA)
|
| MipsSEISelLowering.cpp | 796 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
800 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
802 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
806 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
810 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
|
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 247 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
263 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
387 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
396 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
|
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 151 MachineInstrBuilder NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
185 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
230 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
249 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
268 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
332 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
351 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
370 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
396 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
402 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X)
[all...] |
| SIISelLowering.cpp | 289 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
291 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
293 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
295 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
300 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
311 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
[all...] |
| R600OptimizeVectorRegisters.cpp | 191 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
208 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 131 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
140 BuildMI(MBB, ++J, MI->getDebugLoc(),
|
