| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 203 struct CondCodeOp CondCode;
242 return CondCode.Code;
773 Op->CondCode.Code = Code;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 290 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
364 ISD::CondCode &CCCode, SDLoc dl);
491 ISD::CondCode &CCCode, SDLoc dl);
[all...] |
| SelectionDAG.cpp | 222 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
227 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
234 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
244 return ISD::CondCode(Operation);
251 static int isSignedOp(ISD::CondCode Opcode) {
271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2
[all...] |
| TargetLowering.cpp | 104 ISD::CondCode &CCCode,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 548 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 700 ISD::CondCode CC,
784 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
816 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 554 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
|
| MipsISelLowering.cpp | 457 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
486 static bool invertFPCondCodeUser(Mips::CondCode CC) {
513 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
523 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
554 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86ISelLowering.h | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.cpp | 145 CondCode cvtCondCode(enum sm4_opcode op) const;
242 CondCode
[all...] |
| nv50_ir_peephole.cpp | 764 CondCode cc, ccZ;
770 ccZ = (CondCode)((unsigned int)i->asCmp()->setCond & ~CC_U);
[all...] |
| nv50_ir_lowering_nv50.cpp | 359 CondCode cc = mul->cc;
639 const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 397 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
|
| SIISelLowering.cpp | 420 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 295 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
333 assert(0 && "Invalid setcc condcode !");
|
| R600ISelLowering.cpp | 846 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
869 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.cpp | 145 CondCode cvtCondCode(enum sm4_opcode op) const;
242 CondCode
[all...] |
| nv50_ir_peephole.cpp | 764 CondCode cc, ccZ;
770 ccZ = (CondCode)((unsigned int)i->asCmp()->setCond & ~CC_U);
[all...] |
| nv50_ir_lowering_nv50.cpp | 359 CondCode cc = mul->cc;
639 const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 397 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
|
| SIISelLowering.cpp | 420 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
|
