| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
215 ARMCC::CondCodes Pred, unsigned PredReg,
610 ARMCC::CondCodes
|
| ARMISelLowering.h | 570 ARMCC::CondCodes CC = ARMCC::AL) const;
575 ARMCC::CondCodes Cond) const;
|
| MLxExpansionPass.cpp | 283 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
|
| Thumb2SizeReduction.cpp | 153 bool is2Addr, ARMCC::CondCodes Pred,
294 bool is2Addr, ARMCC::CondCodes Pred,
688 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
785 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | 245 ARMCC::CondCodes CCVal, SDValue CCR,
248 ARMCC::CondCodes CCVal, SDValue CCR,
251 ARMCC::CondCodes CCVal, SDValue CCR,
254 ARMCC::CondCodes CCVal, SDValue CCR,
[all...] |
| ARMFrameLowering.cpp | 123 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
[all...] |
| Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg,
|
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | 616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchFixupPass.cpp | 494 A64CC::CondCodes CC = (A64CC::CondCodes)MI->getOperand(0).getImm();
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| AArch64ISelLowering.h | 219 A64CC::CondCodes Cond) const;
|
| AArch64ISelLowering.cpp | 425 A64CC::CondCodes Cond) const {
[all...] |
| AArch64InstrInfo.cpp | 257 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
|
| /external/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 196 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
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| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 209 O << A64CondCodeToString(static_cast<A64CC::CondCodes>(MO.getImm()));
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 854 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
865 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 170 A64CC::CondCodes Code;
240 A64CC::CondCodes getCondCode() const {
770 static AArch64Operand *CreateCondCode(A64CC::CondCodes Code,
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 70 ARMCC::CondCodes Cond; // Condition for IT block.
322 ARMCC::CondCodes Val;
535 ARMCC::CondCodes getCondCode() const {
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 574 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 706 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
[all...] |
