| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 178 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
290 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
313 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
438 MVT VT) const;
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| Mips16ISelDAGToDAG.cpp | 48 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
227 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
282 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 719 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
[all...] |
| LegalizeFloatTypes.cpp | 35 VT == MVT::f32 ? Call_F32 :
36 VT == MVT::f64 ? Call_F64 :
37 VT == MVT::f80 ? Call_F80 :
38 VT == MVT::f128 ? Call_F128 :
39 VT == MVT::ppcf128 ? Call_PPCF128 :
409 assert(N->getOperand(1).getValueType() == MVT::i32 &&
574 for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
575 t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
576 NVT = (MVT::SimpleValueType)t;
[all...] |
| TargetLowering.cpp | 106 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
114 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
115 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
119 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
120 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
124 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
125 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
129 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32
[all...] |
| InstrEmitter.cpp | 44 while (N && Node->getValueType(N - 1) == MVT::Glue)
46 if (N && Node->getValueType(N - 1) == MVT::Other)
61 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
102 MVT VT = Node->getSimpleValueType(ResNo);
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
301 assert(Op.getValueType() != MVT::Other &&
302 Op.getValueType() != MVT::Glue &
[all...] |
| ResourcePriorityQueue.cpp | 97 MVT VT = ScegN->getSimpleValueType(i);
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
335 MVT VT = SU->getNode()->getSimpleValueType(i);
344 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
488 MVT VT = ScegN->getSimpleValueType(i);
499 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
|
| InstrEmitter.h | 88 MVT VT, DebugLoc DL);
|
| ScheduleDAGSDNodes.cpp | 171 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
175 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
181 VTs.push_back(MVT::Glue);
191 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
204 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
210 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
266 // Cluster loads by adding MVT::Glue outputs and inputs. This also
354 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
364 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
465 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!")
[all...] |
| SelectionDAG.cpp | 529 if (N->getValueType(0) == MVT::Glue)
541 if (N->getValueType(i) == MVT::Glue)
689 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Glue &&
863 Type *Ty = VT == MVT::iPTR ?
873 EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other)),
[all...] |
| SelectionDAGPrinter.cpp | 94 if (VT == MVT::Glue)
96 else if (VT == MVT::Other)
|
| LegalizeVectorOps.cpp | 166 MVT ValVT = ST->getValue().getSimpleValueType();
319 MVT VT = Op.getSimpleValueType();
322 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
358 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
510 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
566 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 245 MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ?
246 MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
247 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
385 Reg = getX86SubSuperRegister(Reg, MVT::i8);
388 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
391 Reg = getX86SubSuperRegister(Reg, MVT::i16);
394 Reg = getX86SubSuperRegister(Reg, MVT::i32);
397 Reg = getX86SubSuperRegister(Reg, MVT::i64)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 293 assert((!N.getNode() || N.getValueType() == MVT::Other) &&
442 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
451 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
459 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
465 SDVTList VTs = getVTList(VT, MVT::Other);
475 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
518 SDVTList VTs = getVTList(MVT::Other, MVT::Glue)
[all...] |
| FunctionLoweringInfo.h | 141 unsigned CreateReg(MVT VT);
|
| SelectionDAGNodes.h | 134 MVT getSimpleValueType() const {
570 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
595 if (UI.getUse().get().getValueType() == MVT::Glue)
614 MVT getSimpleValueType(unsigned ResNo) const {
618 /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
948 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenDAGPatterns.cpp | 32 static inline bool isInteger(MVT::SimpleValueType VT) {
35 static inline bool isFloatingPoint(MVT::SimpleValueType VT) {
38 static inline bool isVector(MVT::SimpleValueType VT) {
41 static inline bool isScalar(MVT::SimpleValueType VT) {
45 EEVT::TypeSet::TypeSet(MVT::SimpleValueType VT, TreePattern &TP) {
46 if (VT == MVT::iAny)
48 else if (VT == MVT::fAny)
50 else if (VT == MVT::vAny)
53 assert((VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR |
[all...] |
| DAGISelMatcherGen.cpp | 24 /// have different associated types, return MVT::Other.
25 static MVT::SimpleValueType getRegisterValueType(Record *R,
28 MVT::SimpleValueType VT = MVT::Other;
614 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
622 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
797 SmallVector<MVT::SimpleValueType, 4> ResultVTs;
[all...] |
| FastISelEmitter.cpp | 175 MVT::SimpleValueType VT,
368 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
369 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
495 MVT::SimpleValueType RetVT = MVT::isVoid;
497 MVT::SimpleValueType VT = RetVT;
604 MVT::SimpleValueType VT = TI->first;
609 MVT::SimpleValueType RetVT = RI->first;
677 OS << "(MVT RetVT";
684 MVT::SimpleValueType RetVT = RI->first
[all...] |
| DAGISelMatcherOpt.cpp | 132 const SmallVectorImpl<MVT::SimpleValueType> &VTs = EN->getVTList();
426 CTM->getType() == MVT::iPTR ||
461 SmallVector<std::pair<MVT::SimpleValueType, Matcher*>, 8> Cases;
467 MVT::SimpleValueType CTMTy = CTM->getType();
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 145 return MVT::i1;
155 MVT VT) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 40 typedef const MVT::SimpleValueType* vt_iterator;
105 for(int i = 0; VTs[i] != MVT::Other; ++i)
119 while (*I != MVT::Other) ++I;
309 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.h | 57 virtual MVT getScalarShiftAmountTy(EVT VT) const;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 87 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
161 MVT VT) const;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 386 if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
394 assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
395 RC->hasType(MVT::f128))
432 if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
440 assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64)
441 || RC->hasType(MVT::f128)
[all...] |
