| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 232 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
346 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
349 Mips::ZERO_64, MVT::i64);
350 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
353 Mips::ZERO, MVT::i32);
354 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
380 MVT::i64);
386 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
389 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
390 CurDAG->getRegister(Mips::ZERO_64, MVT::i64)
[all...] |
| Mips16ISelLowering.cpp | 122 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
123 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
134 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
331 MVT RegVT =
387 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
420 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2)
[all...] |
| FastISel.cpp | 148 MVT VT = RealVT.getSimpleVT();
151 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
183 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
295 MVT PtrVT = TLI.getPointerTy();
359 if (VT == MVT::Other || !VT.isSimple())
368 // MVT::i1 is special. Allow AND, OR, or XOR because they
370 if (VT == MVT::i1 &&
479 MVT VT = TLI.getPointerTy()
[all...] |
| SelectionDAGISel.cpp | 552 if (N->getOperand(i).getValueType() == MVT::Other)
[all...] |
| ScheduleDAGSDNodes.h | 29 /// SDNodes with MVT::Glue operands are grouped along with the flagged
138 MVT ValueType;
144 MVT GetValue() const {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 544 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
780 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64);
785 if (N.getValueType() == MVT::i32 && VT == MVT::i64) {
786 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
791 if (N.getValueType() == MVT::i64 && VT == MVT::i32) {
792 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
818 if (VT == MVT::i32 |
[all...] |
| SystemZISelLowering.h | 126 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
127 return MVT::i32;
130 return MVT::i32;
141 MVT VT) const LLVM_OVERRIDE;
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 498 MVT::SimpleValueType Type;
501 CheckTypeMatcher(MVT::SimpleValueType type, unsigned resno)
504 MVT::SimpleValueType getType() const { return Type; }
527 SmallVector<std::pair<MVT::SimpleValueType, Matcher*>, 8> Cases;
529 SwitchTypeMatcher(const std::pair<MVT::SimpleValueType, Matcher*> *cases,
539 MVT::SimpleValueType getCaseType(unsigned i) const { return Cases[i].first; }
554 MVT::SimpleValueType Type;
556 CheckChildTypeMatcher(unsigned childno, MVT::SimpleValueType type)
560 MVT::SimpleValueType getType() const { return Type; }
770 MVT::SimpleValueType VT
[all...] |
| DAGISelMatcher.cpp | 189 OS.indent(indent) << "CheckValueType MVT::" << TypeName << '\n';
344 static bool TypesAreContradictory(MVT::SimpleValueType T1,
345 MVT::SimpleValueType T2) {
352 if (T1 == MVT::iPTR)
353 return !MVT(T2).isInteger() || MVT(T2).isVector();
355 if (T2 == MVT::iPTR)
356 return !MVT(T1).isInteger() || MVT(T1).isVector();
378 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo())
[all...] |
| IntrinsicEmitter.cpp | 267 static void EncodeFixedValueType(MVT::SimpleValueType VT,
282 default: PrintFatalError("unhandled MVT in intrinsic!");
283 case MVT::f16: return Sig.push_back(IIT_F16);
284 case MVT::f32: return Sig.push_back(IIT_F32);
285 case MVT::f64: return Sig.push_back(IIT_F64);
286 case MVT::Metadata: return Sig.push_back(IIT_METADATA);
287 case MVT::x86mmx: return Sig.push_back(IIT_MMX);
288 // MVT::OtherVT is used to mean the empty struct type here.
289 case MVT::Other: return Sig.push_back(IIT_EMPTYSTRUCT);
312 MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT"))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
39 setOperationAction(ISD::UDIV, MVT::i32, Expand);
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
41 setOperationAction(ISD::UREM, MVT::i32, Expand);
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
169 DAG.getConstantFP(1.0f, MVT::f32),
|
| R600RegisterInfo.cpp | 108 MVT VT) const
112 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
|
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 181 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
182 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
226 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
273 std::pair<unsigned, MVT> SrcLT = TLI->getTypeLegalizationCost(Src);
274 std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(Dst);
374 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
408 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(Src);
461 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(RetTy);
494 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(Tp);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 346 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
422 MVT VT) const;
637 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
642 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
643 MVT &LocVT,
648 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
649 MVT &LocVT,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
39 setOperationAction(ISD::UDIV, MVT::i32, Expand);
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
41 setOperationAction(ISD::UREM, MVT::i32, Expand);
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
169 DAG.getConstantFP(1.0f, MVT::f32),
|
| R600RegisterInfo.cpp | 108 MVT VT) const
112 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 115 MVT VT;
126 InputArg() : VT(MVT::Other), Used(false) {}
140 MVT VT;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 76 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
102 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 71 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
74 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 355 MVT VT) const;
372 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
398 findRepresentativeClass(MVT VT) const;
413 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
414 void addDRTypeForNEON(MVT VT);
415 void addQRTypeForNEON(MVT VT);
|
| /external/llvm/lib/Target/R600/ |
| R600RegisterInfo.cpp | 82 MVT VT) const {
85 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 511 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
554 virtual bool isSafeMemOpType(MVT VT) const;
643 MVT VT) const;
718 return !X86ScalarSSEf64 || VT == MVT::f80;
728 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
729 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
741 return isTargetFTOL() && VT == MVT::i64;
763 findRepresentativeClass(MVT VT) const;
[all...] |
| X86RegisterInfo.h | 137 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
138 unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
