| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/ |
| i830_vtbl.c | 306 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
307 OUT_BATCH(0);
309 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
310 OUT_BATCH(0);
312 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
313 OUT_BATCH(0);
315 OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
316 OUT_BATCH(FOGFUNC_ENABLE |
318 OUT_BATCH(0);
319 OUT_BATCH(0)
[all...] |
| i915_vtbl.c | 182 OUT_BATCH(_3DSTATE_AA_CMD |
187 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
188 OUT_BATCH(0);
190 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
191 OUT_BATCH(0);
193 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
194 OUT_BATCH(0);
197 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
206 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
207 OUT_BATCH(0)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i830_vtbl.c | 306 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
307 OUT_BATCH(0);
309 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
310 OUT_BATCH(0);
312 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
313 OUT_BATCH(0);
315 OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
316 OUT_BATCH(FOGFUNC_ENABLE |
318 OUT_BATCH(0);
319 OUT_BATCH(0)
[all...] |
| i915_vtbl.c | 182 OUT_BATCH(_3DSTATE_AA_CMD |
187 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
188 OUT_BATCH(0);
190 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
191 OUT_BATCH(0);
193 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
194 OUT_BATCH(0);
197 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
206 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
207 OUT_BATCH(0)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| gen7_viewport_state.c | 70 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL << 16 | (2 - 2));
71 OUT_BATCH(brw->sf.vp_offset);
91 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
92 OUT_BATCH(brw->cc.vp_offset);
|
| gen7_sf_state.c | 130 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
131 OUT_BATCH(dw1);
135 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
138 OUT_BATCH(dw10); /* point sprite texcoord bitmask */
139 OUT_BATCH(dw11); /* constant interp bitmask */
140 OUT_BATCH(0); /* wrapshortest enables 0-7 */
141 OUT_BATCH(0); /* wrapshortest enables 8-15 */
294 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
295 OUT_BATCH(dw1);
296 OUT_BATCH(dw2)
[all...] |
| gen6_sf_state.c | 334 OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
335 OUT_BATCH(dw1);
336 OUT_BATCH(dw2);
337 OUT_BATCH(dw3);
338 OUT_BATCH(dw4);
343 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
345 OUT_BATCH(dw16); /* point sprite texcoord bitmask */
346 OUT_BATCH(dw17); /* constant interp bitmask */
347 OUT_BATCH(0); /* wrapshortest enables 0-7 */
348 OUT_BATCH(0); /* wrapshortest enables 8-15 *
[all...] |
| gen6_urb.c | 94 OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
95 OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
97 OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
|
| gen6_viewport_state.c | 115 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
119 OUT_BATCH(brw->clip.vp_offset);
120 OUT_BATCH(brw->sf.vp_offset);
121 OUT_BATCH(brw->cc.vp_offset);
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_cmdbuf.h | 45 #define OUT_BATCH(data) \
76 * The number of (direct or indirect) OUT_BATCH calls between the previous
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
96 OUT_BATCH((val))
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
|
| radeon_ioctl.h | 161 OUT_BATCH(CP_PACKET2); \
162 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
166 OUT_BATCH(CP_PACKET2); \
167 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen7_viewport_state.c | 70 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL << 16 | (2 - 2));
71 OUT_BATCH(brw->sf.vp_offset);
91 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
92 OUT_BATCH(brw->cc.vp_offset);
|
| gen7_sf_state.c | 130 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
131 OUT_BATCH(dw1);
135 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
138 OUT_BATCH(dw10); /* point sprite texcoord bitmask */
139 OUT_BATCH(dw11); /* constant interp bitmask */
140 OUT_BATCH(0); /* wrapshortest enables 0-7 */
141 OUT_BATCH(0); /* wrapshortest enables 8-15 */
294 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
295 OUT_BATCH(dw1);
296 OUT_BATCH(dw2)
[all...] |
| gen6_sf_state.c | 334 OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
335 OUT_BATCH(dw1);
336 OUT_BATCH(dw2);
337 OUT_BATCH(dw3);
338 OUT_BATCH(dw4);
343 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
345 OUT_BATCH(dw16); /* point sprite texcoord bitmask */
346 OUT_BATCH(dw17); /* constant interp bitmask */
347 OUT_BATCH(0); /* wrapshortest enables 0-7 */
348 OUT_BATCH(0); /* wrapshortest enables 8-15 *
[all...] |
| gen6_urb.c | 94 OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
95 OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
97 OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
|
| gen6_viewport_state.c | 115 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
119 OUT_BATCH(brw->clip.vp_offset);
120 OUT_BATCH(brw->sf.vp_offset);
121 OUT_BATCH(brw->cc.vp_offset);
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_cmdbuf.h | 45 #define OUT_BATCH(data) \
76 * The number of (direct or indirect) OUT_BATCH calls between the previous
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
96 OUT_BATCH((val))
101 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
|
| radeon_ioctl.h | 161 OUT_BATCH(CP_PACKET2); \
162 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
166 OUT_BATCH(CP_PACKET2); \
167 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
| i915_prim_vbuf.c | 396 OUT_BATCH((i+0) | (i+1) << 16);
398 OUT_BATCH(i);
403 OUT_BATCH((i-1) | (i+0) << 16);
404 OUT_BATCH((i-1) | ( start) << 16);
409 OUT_BATCH((i+0) | (i+1) << 16);
410 OUT_BATCH((i+3) | (i+1) << 16);
411 OUT_BATCH((i+2) | (i+3) << 16);
416 OUT_BATCH((i+0) | (i+1) << 16);
417 OUT_BATCH((i+3) | (i+2) << 16);
418 OUT_BATCH((i+0) | (i+3) << 16)
[all...] |
| i915_batch.h | 38 #define OUT_BATCH(dword) \
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_prim_vbuf.c | 396 OUT_BATCH((i+0) | (i+1) << 16);
398 OUT_BATCH(i);
403 OUT_BATCH((i-1) | (i+0) << 16);
404 OUT_BATCH((i-1) | ( start) << 16);
409 OUT_BATCH((i+0) | (i+1) << 16);
410 OUT_BATCH((i+3) | (i+1) << 16);
411 OUT_BATCH((i+2) | (i+3) << 16);
416 OUT_BATCH((i+0) | (i+1) << 16);
417 OUT_BATCH((i+3) | (i+2) << 16);
418 OUT_BATCH((i+0) | (i+3) << 16)
[all...] |
| i915_batch.h | 38 #define OUT_BATCH(dword) \
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_ioctl.h | 148 OUT_BATCH(CP_PACKET2); \
149 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
153 OUT_BATCH(CP_PACKET2); \
154 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
|
| r200_cmdbuf.c | 132 OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
144 OUT_BATCH(R200_VF_PRIM_WALK_IND |
150 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
152 OUT_BATCH((vertex_count + 1)/2);
215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
216 OUT_BATCH(count);
233 OUT_BATCH(1);
234 OUT_BATCH(vertex_size | (vertex_size << 8));
252 OUT_BATCH(nr)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_ioctl.h | 148 OUT_BATCH(CP_PACKET2); \
149 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
153 OUT_BATCH(CP_PACKET2); \
154 OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
|
