| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_cmdbuf.c | 132 OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
144 OUT_BATCH(R200_VF_PRIM_WALK_IND |
150 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
152 OUT_BATCH((vertex_count + 1)/2);
215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
216 OUT_BATCH(count);
233 OUT_BATCH(1);
234 OUT_BATCH(vertex_size | (vertex_size << 8));
252 OUT_BATCH(nr)
[all...] |
| r200_state_init.c | 281 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
282 OUT_BATCH(0); \
283 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
284 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
285 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
297 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
298 OUT_BATCH(0); \
299 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
300 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
301 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1));
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| gen6_scissor_state.c | 83 OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
84 OUT_BATCH(scissor_state_offset);
|
| brw_draw.c | 189 OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
192 OUT_BATCH(verts_per_instance);
193 OUT_BATCH(start_vertex_location);
194 OUT_BATCH(prim->num_instances);
195 OUT_BATCH(0); // start instance location
196 OUT_BATCH(base_vertex_location);
246 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
247 OUT_BATCH(hw_prim | vertex_access_type);
248 OUT_BATCH(verts_per_instance);
249 OUT_BATCH(start_vertex_location)
[all...] |
| gen6_sol.c | 139 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
140 OUT_BATCH(0);
141 OUT_BATCH(brw->sol.svbi_0_starting_index); /* BRW_NEW_SOL_INDICES */
142 OUT_BATCH(brw->sol.svbi_0_max_index); /* BRW_NEW_SOL_INDICES */
|
| brw_primitive_restart.c | 202 OUT_BATCH(_3DSTATE_VF << 16 | cut_index_setting | (2 - 2));
203 OUT_BATCH(ctx->Array.RestartIndex);
|
| brw_curbe.c | 156 OUT_BATCH(CMD_CS_URB_STATE << 16 | (2-2));
160 OUT_BATCH(0);
164 OUT_BATCH((brw->urb.csize - 1) << 4 | brw->urb.nr_cs_entries);
343 OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2));
344 OUT_BATCH(0);
346 OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
|
| brw_draw_upload.c | 588 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
590 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
595 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
600 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
619 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
639 OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
644 OUT_BATCH(0);
645 OUT_BATCH(buffer->step_rate);
670 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
713 OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT)
[all...] |
| gen6_cc.c | 251 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
252 OUT_BATCH(brw->cc.blend_state_offset | 1);
253 OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
254 OUT_BATCH(brw->cc.state_offset | 1);
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen6_scissor_state.c | 83 OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
84 OUT_BATCH(scissor_state_offset);
|
| brw_draw.c | 189 OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
192 OUT_BATCH(verts_per_instance);
193 OUT_BATCH(start_vertex_location);
194 OUT_BATCH(prim->num_instances);
195 OUT_BATCH(0); // start instance location
196 OUT_BATCH(base_vertex_location);
246 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
247 OUT_BATCH(hw_prim | vertex_access_type);
248 OUT_BATCH(verts_per_instance);
249 OUT_BATCH(start_vertex_location)
[all...] |
| gen6_sol.c | 139 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
140 OUT_BATCH(0);
141 OUT_BATCH(brw->sol.svbi_0_starting_index); /* BRW_NEW_SOL_INDICES */
142 OUT_BATCH(brw->sol.svbi_0_max_index); /* BRW_NEW_SOL_INDICES */
|
| brw_primitive_restart.c | 202 OUT_BATCH(_3DSTATE_VF << 16 | cut_index_setting | (2 - 2));
203 OUT_BATCH(ctx->Array.RestartIndex);
|
| brw_curbe.c | 156 OUT_BATCH(CMD_CS_URB_STATE << 16 | (2-2));
160 OUT_BATCH(0);
164 OUT_BATCH((brw->urb.csize - 1) << 4 | brw->urb.nr_cs_entries);
343 OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2));
344 OUT_BATCH(0);
346 OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
|
| brw_draw_upload.c | 588 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
590 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
595 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
600 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
619 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
639 OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
644 OUT_BATCH(0);
645 OUT_BATCH(buffer->step_rate);
670 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
713 OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT)
[all...] |
| gen6_cc.c | 251 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
252 OUT_BATCH(brw->cc.blend_state_offset | 1);
253 OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
254 OUT_BATCH(brw->cc.state_offset | 1);
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
244 OUT_BATCH(0); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
246 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
247 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
255 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
256 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
372 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
376 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0))
[all...] |
| radeon_blit.c | 306 OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD | (13 << 16));
307 OUT_BATCH(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0);
308 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
244 OUT_BATCH(0); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
246 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
247 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
255 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
256 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
372 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
376 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0))
[all...] |
| radeon_blit.c | 306 OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD | (13 << 16));
307 OUT_BATCH(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0);
308 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_state_init.c | 281 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
282 OUT_BATCH(0); \
283 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
284 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
285 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
297 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
298 OUT_BATCH(0); \
299 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
300 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
301 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1));
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/ |
| intel_tris.c | 109 OUT_BATCH(0);
266 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | cmd | (len - 2));
272 OUT_BATCH((intel->vertex_size << S1_VERTEX_WIDTH_SHIFT) |
276 OUT_BATCH(_3DPRIMITIVE |
281 OUT_BATCH(offset / (intel->vertex_size * 4));
287 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
300 OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
305 OUT_BATCH(_3DPRIMITIVE |
310 OUT_BATCH(0); /* Beginning vertex index */
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_tris.c | 109 OUT_BATCH(0);
266 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | cmd | (len - 2));
272 OUT_BATCH((intel->vertex_size << S1_VERTEX_WIDTH_SHIFT) |
276 OUT_BATCH(_3DPRIMITIVE |
281 OUT_BATCH(offset / (intel->vertex_size * 4));
287 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
300 OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
305 OUT_BATCH(_3DPRIMITIVE |
310 OUT_BATCH(0); /* Beginning vertex index */
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/ |
| intel_batchbuffer.h | 157 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel, d)
|
| /external/mesa3d/src/mesa/drivers/dri/intel/ |
| intel_batchbuffer.h | 157 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel, d)
|
