| /external/llvm/lib/CodeGen/ |
| StrongPHIElimination.cpp | 139 // Merges the live interval of Reg into NewReg and renames Reg to NewReg
140 // everywhere that Reg appears. Requires Reg and NewReg to have non-
142 void MergeLIsAndRename(unsigned Reg, unsigned NewReg);
217 static MachineOperand *findLastUse(MachineBasicBlock *MBB, unsigned Reg) {
227 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
406 void StrongPHIElimination::addReg(unsigned Reg) {
407 Node *&N = RegNodeMap[Reg];
409 N = new (Allocator) Node(Reg);
[all...] |
| TailDuplication.cpp | 329 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB,
331 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
427 unsigned Reg = MO.getReg();
428 if (!TargetRegisterInfo::isVirtualRegister(Reg))
431 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
434 LocalVRMap.insert(std::make_pair(Reg, NewReg));
435 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
436 AddSSAUpdateEntry(Reg, NewReg, PredBB);
438 DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg);
[all...] |
| RegAllocGreedy.cpp | 138 return ExtraRegInfo[VirtReg.reg].Stage;
143 ExtraRegInfo[VirtReg.reg].Stage = Stage;
150 unsigned Reg = (*Begin)->reg;
151 if (ExtraRegInfo[Reg].Stage == RS_New)
152 ExtraRegInfo[Reg].Stage = NewStage;
197 void reset(InterferenceCache &Cache, unsigned Reg) {
198 PhysReg = Reg;
200 Intf.setPhysReg(Cache, Reg);
401 // The queue holds (size, reg) pairs
[all...] |
| EarlyIfConversion.cpp | 235 unsigned Reg = MO->getReg();
238 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
239 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
242 if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
244 MachineInstr *DefMI = MRI->getVRegDef(Reg);
290 unsigned Reg = MO->getReg();
291 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
293 // I clobbers Reg, so it isn't live before I.
295 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
297 // Unless I reads Reg
[all...] |
| RegAllocPBQP.cpp | 203 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
204 if (mri->def_empty(Reg))
206 pregs.insert(Reg);
207 mri->setPhysRegUsed(Reg);
453 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
454 if (mri->reg_nodbg_empty(Reg))
456 LiveInterval *li = &lis->getInterval(Reg);
462 vregsToAlloc.insert(li->reg);
[all...] |
| RegisterClassInfo.cpp | 56 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
57 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
| CalcSpillWeights.cpp | 53 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
54 if (MRI.reg_nodbg_empty(Reg))
56 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
61 // Return the preferred allocation register for reg, given a COPY instruction.
62 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
66 if (mi->getOperand(0).getReg() == reg) {
82 const TargetRegisterClass *rc = mri.getRegClass(reg);
88 // reg:sub should match the physreg hreg.
128 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
133 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 98 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
174 // Create the reg, emit the copy.
199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
201 return Reg;
215 // If the specific node value is only used by a CopyToReg and the dest reg
236 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
237 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
238 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
240 VRBase = Reg;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 318 unsigned Reg = I->getReg();
320 // If Reg is a double precision register, emit two cfa_offsets,
322 if (Mips::AFGR64RegClass.contains(Reg)) {
324 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
326 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
336 // Reg is either in GPR32 or FGR32.
338 CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
361 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
362 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
450 unsigned Reg = CSI[i].getReg()
[all...] |
| Mips16FrameLowering.cpp | 117 unsigned Reg = CSI[i].getReg();
118 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
121 EntryBlock->addLiveIn(Reg);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 548 llvm_unreachable("Impossible reg-to-reg copy");
601 unsigned Reg = 0;
604 Reg = PPC::CR0;
607 Reg = PPC::CR1;
610 Reg = PPC::CR2;
613 Reg = PPC::CR3;
616 Reg = PPC::CR4;
619 Reg = PPC::CR5;
622 Reg = PPC::CR6
[all...] |
| PPCRegisterInfo.h | 77 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 65 unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
66 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
|
| /external/llvm/lib/Target/ARM/ |
| ARMMachineFunctionInfo.h | 273 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.cpp | 155 void UnwindOpcodeAssembler::EmitSetSP(uint16_t Reg) {
156 EmitInt8(UNWIND_OPCODE_SET_VSP | Reg);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 74 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
76 MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(Reg, true), 0);
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/X11/ |
| Xregion.h | 114 #define MEMCHECK(reg, rect, firstrect){\
115 if ((reg)->numRects >= ((reg)->size - 1)){\
117 ((char *)(firstrect), (unsigned) (2 * (sizeof(BOX)) * ((reg)->size)));\
120 (reg)->size *= 2;\
121 (rect) = &(firstrect)[(reg)->numRects];\
129 #define CHECK_PREVIOUS(Reg, R, Rx1, Ry1, Rx2, Ry2)\
130 (!(((Reg)->numRects > 0)&&\
137 #define ADDRECT(reg, r, rx1, ry1, rx2, ry2){\
139 CHECK_PREVIOUS((reg), (r), (rx1), (ry1), (rx2), (ry2))){
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| Xregion.h | 114 #define MEMCHECK(reg, rect, firstrect){\
115 if ((reg)->numRects >= ((reg)->size - 1)){\
117 ((char *)(firstrect), (unsigned) (2 * (sizeof(BOX)) * ((reg)->size)));\
120 (reg)->size *= 2;\
121 (rect) = &(firstrect)[(reg)->numRects];\
129 #define CHECK_PREVIOUS(Reg, R, Rx1, Ry1, Rx2, Ry2)\
130 (!(((Reg)->numRects > 0)&&\
137 #define ADDRECT(reg, r, rx1, ry1, rx2, ry2){\
139 CHECK_PREVIOUS((reg), (r), (rx1), (ry1), (rx2), (ry2))){
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| Xregion.h | 114 #define MEMCHECK(reg, rect, firstrect){\
115 if ((reg)->numRects >= ((reg)->size - 1)){\
117 ((char *)(firstrect), (unsigned) (2 * (sizeof(BOX)) * ((reg)->size)));\
120 (reg)->size *= 2;\
121 (rect) = &(firstrect)[(reg)->numRects];\
129 #define CHECK_PREVIOUS(Reg, R, Rx1, Ry1, Rx2, Ry2)\
130 (!(((Reg)->numRects > 0)&&\
137 #define ADDRECT(reg, r, rx1, ry1, rx2, ry2){\
139 CHECK_PREVIOUS((reg), (r), (rx1), (ry1), (rx2), (ry2))){
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 70 OS << markup("<reg:")
248 // a single GPRPair reg operand is used in the .td file to replace the two
255 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
256 if (MRC.contains(Reg)) {
263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
283 unsigned Reg = Op.getReg();
284 printRegName(O, Reg);
336 // REG 0 0 - e.g. R5
337 // REG REG 0,SH_OPC - e.g. R5, ROR R
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 42 unsigned Reg;
|
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.h | 89 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
|
| SIISelLowering.h | 66 unsigned Reg, EVT VT) const;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 57 // Try to get first reg.
58 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
59 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
68 // Try to get second reg.
69 if (unsigned Reg = State.AllocateReg(RegList, 6))
70 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
87 unsigned Reg = 0;
91 Reg = SP::I0 + Offset/8;
94 Reg = SP::D0 + Offset/8;
97 Reg = SP::F1 + Offset/4
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineFrameInfo.h | 38 unsigned Reg;
43 : Reg(R), FrameIdx(FI) {}
46 unsigned getReg() const { return Reg; }
|
