| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 216 SDNode *N = SU->getNode();
237 SmallVector<SDNode*, 2> NewNodes;
245 SDNode *LoadNode = NewNodes[0];
391 SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(NULL));
395 SUnit *CopyToSU = newSUnit(static_cast<SDNode *>(NULL));
433 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
484 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
654 std::vector<SDNode*> Sequence;
655 DenseMap<SDNode*, SDNode*> GluedMap; // Cache glue to its use
[all...] |
| SelectionDAGISel.cpp | 269 SDNode *Node) const {
535 SmallPtrSet<SDNode*, 128> VisitedNodes;
536 SmallVector<SDNode*, 128> Worklist;
544 SDNode *N = Worklist.pop_back_val();
748 virtual void NodeDeleted(SDNode *N, SDNode *E) {
783 SDNode *Node = --ISelPosition;
790 SDNode *ResNode = Select(Node);
[all...] |
| SelectionDAG.cpp | 63 void SelectionDAG::DAGUpdateListener::NodeDeleted(SDNode*, SDNode*) {}
64 void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode*) {}
97 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
145 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
185 bool ISD::isScalarToVector(const SDNode *N) {
206 bool ISD::allOperandsUndef(const SDNode *N) {
320 // SDNode Profile Support
363 /// AddNodeIDCustom - If this is an SDNode with special info, add this info to
365 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
[all...] |
| LegalizeIntegerTypes.cpp | 35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N)
[all...] |
| LegalizeVectorTypes.cpp | 33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
128 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
135 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N)
[all...] |
| LegalizeTypes.cpp | 73 SmallVector<SDNode*, 16> NewNodes;
88 for (SDNode::use_iterator UI = I->use_begin(), UE = I->use_end();
169 SDNode *N = NewNodes[i];
170 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
212 SDNode *N = Worklist.back();
321 SDNode *M = AnalyzeNewNode(N);
351 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
353 SDNode *User = *UI;
449 SDNode *DAGTypeLegalizer::AnalyzeNewNode(SDNode *N)
[all...] |
| DAGCombiner.cpp | 83 SmallPtrSet<SDNode*, 64> WorkListContents;
84 SmallVector<SDNode*, 64> WorkListOrder;
93 void AddUsersToWorkList(SDNode *N) {
94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
101 SDValue visit(SDNode *N);
106 void AddToWorkList(SDNode *N) {
113 void removeFromWorkList(SDNode *N) {
117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 131 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
263 SDNode *tryRISBGZero(SDNode *N);
267 SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
276 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
279 bool storeLoadCanUseMVC(SDNode *N) const;
293 virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 88 SDNode *Select(SDNode *N);
91 bool hasNoVMLxHazardUse(SDNode *N) const;
133 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
135 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
137 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
146 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
147 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
174 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N
[all...] |
| ARMBaseInstrInfo.h | 151 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
162 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
227 SDNode *DefNode, unsigned DefIdx,
228 SDNode *UseNode, unsigned UseIdx) const;
272 SDNode *Node) const;
|
| ARMISelLowering.h | 262 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
280 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
282 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
283 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
324 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
332 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
383 Sched::Preference getSchedulingPreference(SDNode *N) const;
544 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 173 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
174 SmallVectorImpl<SDNode*> &NewNodes) const {
187 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| AMDGPUInstrInfo.h | 104 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
105 SmallVectorImpl<SDNode *> &NewNodes) const;
109 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| /external/llvm/include/llvm/CodeGen/ |
| Analysis.h | 29 class SDNode;
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.cpp | 153 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
154 SmallVectorImpl<SDNode*> &NewNodes) const {
167 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| AMDGPUInstrInfo.h | 106 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
107 SmallVectorImpl<SDNode *> &NewNodes) const;
111 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| R600ISelLowering.h | 30 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
31 void ReplaceNodeResults(SDNode * N,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 173 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
174 SmallVectorImpl<SDNode*> &NewNodes) const {
187 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| AMDGPUInstrInfo.h | 104 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
105 SmallVectorImpl<SDNode *> &NewNodes) const;
109 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 450 bool isVEXTRACT128Index(SDNode *N);
455 bool isVINSERT128Index(SDNode *N);
460 bool isVEXTRACT256Index(SDNode *N);
465 bool isVINSERT256Index(SDNode *N);
470 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
475 unsigned getInsertVINSERT128Immediate(SDNode *N);
480 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
485 unsigned getInsertVINSERT256Immediate(SDNode *N);
568 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
572 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
[all...] |
| X86InstrInfo.h | 309 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
310 SmallVectorImpl<SDNode*> &NewNodes) const;
327 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
338 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 98 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
103 SDNode *getGlobalBaseReg();
107 SDNode *Select(SDNode *N);
109 SDNode *SelectBitfieldInsert(SDNode *N);
183 SDNode *SelectSETCC(SDNode *N);
255 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
281 static bool isIntS16Immediate(SDNode *N, short &Imm)
[all...] |
| PPCISelLowering.h | 314 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
323 bool isAllNegativeZeroVector(SDNode *N);
327 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
333 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
354 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
377 Sched::Preference getSchedulingPreference(SDNode *N) const;
386 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
389 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 180 virtual void LowerOperationWrapper(SDNode *N,
190 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
200 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
254 const SDNode *CallNode,
261 bool IsSoftFloat, const SDNode *CallNode,
313 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
318 const SDNode *CallNode, const Type *RetTy) const;
341 const SDNode *CallNode, const Type *RetTy) const;
|
| MipsSEISelDAGToDAG.cpp | 216 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
218 SDNode *Node) const {
229 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
230 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
317 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
325 SDNode *Result;
378 SDNode *RegOpnd;
418 SDNode *Rdhwr =
437 SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL
[all...] |
