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    Searched refs:addImm (Results 76 - 100 of 104) sorted by null

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  /external/llvm/lib/Target/SystemZ/
SystemZFrameLowering.cpp 183 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
254 MIB.addImm(StartOffset);
305 .addReg(Reg).addImm(ThisVal);
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 435 Hexagon::subreg_hireg))).addImm(0);
441 Hexagon::subreg_hireg))).addImm(0);
487 .addFrameIndex(FI).addImm(0)
491 .addFrameIndex(FI).addImm(0)
495 .addFrameIndex(FI).addImm(0)
532 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
535 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
538 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
    [all...]
HexagonNewValueJump.cpp 630 .addImm(cmpOp2)
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 199 .addImm((ME+1) & 31)
200 .addImm((MB-1) & 31);
410 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
    [all...]
  /external/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 106 MIB.addImm(Cond[i].getImm());
Mips16ISelDAGToDAG.cpp 87 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
Mips16ISelLowering.cpp 653 .addImm(MI->getOperand(4).getImm());
714 .addImm(imm);
758 TII->get(SltOpc)).addReg(regX).addImm(Imm);
MipsCodeEmitter.cpp 317 .addReg(Mips::ZERO).addImm(0);
MipsSEISelLowering.cpp 801 .addReg(Mips::ZERO).addImm(0);
807 .addReg(Mips::ZERO).addImm(1);
  /external/llvm/lib/Target/X86/
X86FastISel.cpp 249 TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1);
319 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
924 .addImm(Op1C->getSExtValue());
    [all...]
X86InstrInfo.cpp     [all...]
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.h 323 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
Thumb1FrameLowering.cpp 175 .addFrameIndex(FramePtrSpillFI).addImm(0)
Thumb2SizeReduction.cpp 502 MIB.addImm(OffsetImm / Scale);
560 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
    [all...]
  /external/llvm/lib/Target/R600/
AMDGPUIndirectAddressing.cpp 301 Sequence.addImm(TII->getRegisterInfo().getIndirectSubReg(Addr));
SIInsertWaits.cpp 294 .addImm((Counts.Named.VM & 0xF) |
SIInstrInfo.cpp 205 MIB.addImm(Imm);
R600OptimizeVectorRegisters.cpp 195 .addImm(Chan);
  /external/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 394 .addReg(incr).addReg(dest).addImm(0);
397 .addReg(dest).addReg(incr).addImm(0);
486 .addReg(incr).addReg(oldval).addImm(0);
490 .addReg(oldval).addReg(incr).addImm(Cond);
564 .addReg(dest).addReg(oldval).addImm(0);
566 .addImm(A64CC::NE).addMBB(exitMBB);
652 .addImm(0);
654 .addImm(CondCode)
666 .addImm(0);
680 .addImm(0)
    [all...]
AArch64FrameLowering.cpp 508 .addImm(0) // address-register offset
  /external/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp 141 TII->get(SP::UNIMP)).addImm(structSize);
  /external/llvm/lib/CodeGen/
RegAllocFast.cpp 313 .addFrameIndex(FI).addImm(Offset).addMetadata(MDPtr);
867 .addFrameIndex(SS).addImm(Offset).addMetadata(MDPtr);
    [all...]
LiveDebugVariables.cpp     [all...]

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