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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
si_state_streamout.c 70 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
71 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
73 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
75 cs->buf[cs->cdw++] = strides[i] >> 2; /* VTX_STRIDE (in DW) */
76 cs->buf[cs->cdw++] = 0; /* BUFFER_BASE */
78 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
79 cs->buf[cs->cdw++] =
85 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
86 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
88 cs->buf[cs->cdw++] = 0; /* unused *
    [all...]
r600_hw_context.c 85 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
86 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
87 cs->buf[cs->cdw++] = va;
88 cs->buf[cs->cdw++] = va >> 32;
90 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
91 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
123 num_dw += ctx->cs->cdw;
189 if (!cs->cdw)
208 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
209 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)
    [all...]
radeonsi_pm4.c 213 memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
216 cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
219 cs->cdw += state->ndw;
  /external/mesa3d/src/gallium/drivers/radeonsi/
si_state_streamout.c 70 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
71 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
73 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
75 cs->buf[cs->cdw++] = strides[i] >> 2; /* VTX_STRIDE (in DW) */
76 cs->buf[cs->cdw++] = 0; /* BUFFER_BASE */
78 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
79 cs->buf[cs->cdw++] =
85 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
86 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
88 cs->buf[cs->cdw++] = 0; /* unused *
    [all...]
r600_hw_context.c 85 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
86 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
87 cs->buf[cs->cdw++] = va;
88 cs->buf[cs->cdw++] = va >> 32;
90 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
91 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
123 num_dw += ctx->cs->cdw;
189 if (!cs->cdw)
208 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
209 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)
    [all...]
radeonsi_pm4.c 213 memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
216 cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
219 cs->cdw += state->ndw;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/
r300_cs.h 49 assert(size <= (RADEON_MAX_CMDBUF_DWORDS - cs_copy->cdw)); \
75 cs_copy->buf[cs_copy->cdw++] = (value); \
99 memcpy(cs_copy->buf + cs_copy->cdw, values, count * 4); \
100 cs_copy->cdw += count; \
123 memcpy(cs_copy->buf + cs_copy->cdw, (values), (count) * 4); \
124 cs_copy->cdw += (count); \
  /external/mesa3d/src/gallium/drivers/r300/
r300_cs.h 49 assert(size <= (RADEON_MAX_CMDBUF_DWORDS - cs_copy->cdw)); \
75 cs_copy->buf[cs_copy->cdw++] = (value); \
99 memcpy(cs_copy->buf + cs_copy->cdw, values, count * 4); \
100 cs_copy->cdw += count; \
123 memcpy(cs_copy->buf + cs_copy->cdw, (values), (count) * 4); \
124 cs_copy->cdw += (count); \
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/
r600_query.c 111 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
112 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
113 cs->buf[cs->cdw++] = va;
114 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
120 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
121 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
122 cs->buf[cs->cdw++] = va;
123 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
126 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
127 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)
    [all...]
r600_hw_context.c 84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
124 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
125 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
649 num_dw += ctx->cs->cdw;
845 start_dword = cs->cdw;
    [all...]
evergreen_hw_context.c 782 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
783 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
784 cs->buf[cs->cdw++] = 0;
786 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
787 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
789 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
790 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
791 cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
792 cs->buf[cs->cdw++] = 0;
793 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value *
    [all...]
evergreen_compute_internal.c 66 ctx->cs->buf[ctx->cs->cdw++] = value;
180 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CONFIG_REG, num, 0);
181 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
184 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CONTEXT_REG, num, 0);
185 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
188 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_RESOURCE, num, 0);
189 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_RESOURCE_OFFSET) >> 2;
192 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_SAMPLER, num, 0);
193 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_SAMPLER_OFFSET) >> 2;
196 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CTL_CONST, num, 0)
    [all...]
r600_state_common.c 42 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
43 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
44 cs->cdw += cb->atom.num_dw;
66 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
67 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
68 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
69 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
70 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
78 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
79 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)
    [all...]
r600_pipe.h 795 cs->buf[cs->cdw++] = value;
800 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
801 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
802 cs->cdw += num;
808 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
809 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
810 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
816 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
817 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
818 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2
    [all...]
  /external/mesa3d/src/gallium/drivers/r600/
r600_query.c 111 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
112 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
113 cs->buf[cs->cdw++] = va;
114 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
120 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
121 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
122 cs->buf[cs->cdw++] = va;
123 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
126 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
127 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)
    [all...]
r600_hw_context.c 84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
124 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
125 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
649 num_dw += ctx->cs->cdw;
845 start_dword = cs->cdw;
    [all...]
evergreen_hw_context.c 782 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
783 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
784 cs->buf[cs->cdw++] = 0;
786 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
787 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
789 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
790 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
791 cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
792 cs->buf[cs->cdw++] = 0;
793 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value *
    [all...]
evergreen_compute_internal.c 66 ctx->cs->buf[ctx->cs->cdw++] = value;
180 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CONFIG_REG, num, 0);
181 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
184 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CONTEXT_REG, num, 0);
185 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
188 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_RESOURCE, num, 0);
189 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_RESOURCE_OFFSET) >> 2;
192 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_SAMPLER, num, 0);
193 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_SAMPLER_OFFSET) >> 2;
196 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CTL_CONST, num, 0)
    [all...]
r600_state_common.c 42 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
43 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
44 cs->cdw += cb->atom.num_dw;
66 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
67 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
68 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
69 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
70 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
78 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
79 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)
    [all...]
r600_pipe.h 795 cs->buf[cs->cdw++] = value;
800 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
801 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
802 cs->cdw += num;
808 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
809 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
810 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
816 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
817 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
818 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/winsys/radeon/drm/
radeon_drm_cs.c 197 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
360 assert(cs->base.cdw == 0);
361 if (cs->base.cdw != 0) {
450 if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {
462 if (cs->base.cdw && cs->base.cdw <= RADEON_MAX_CMDBUF_DWORDS) {
465 cs->cst->chunks[0].length_dw = cs->base.cdw;
501 cs->base.cdw = 0;
  /external/mesa3d/src/gallium/winsys/radeon/drm/
radeon_drm_cs.c 197 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
360 assert(cs->base.cdw == 0);
361 if (cs->base.cdw != 0) {
450 if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {
462 if (cs->base.cdw && cs->base.cdw <= RADEON_MAX_CMDBUF_DWORDS) {
465 cs->cst->chunks[0].length_dw = cs->base.cdw;
501 cs->base.cdw = 0;
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
radeon_cmdbuf.h 109 if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
radeon_common.c 476 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) {
568 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
571 if (!radeon->cmdbuf.cs->cdw) {
593 fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw);
600 if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved))
606 if (radeon->cmdbuf.cs->cdw)
671 if (rmesa->cmdbuf.cs->cdw) {
711 if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size
714 assert(rmesa->cmdbuf.cs->cdw);
784 n, rmesa->cmdbuf.cs->cdw, function, line)
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_cmdbuf.h 109 if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )

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