| /external/llvm/include/llvm/MC/MCParser/ |
| MCParsedAsmOperand.h | 49 virtual unsigned getReg() const = 0;
|
| /external/llvm/include/llvm/MC/ |
| MachineLocation.h | 50 unsigned getReg() const { return Register; }
|
| /external/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 69 unsigned Reg = MO.getReg();
127 unsigned Reg = MO.getReg();
155 unsigned Reg = MO.getReg();
174 unsigned Reg = MO.getReg();
|
| MachineSSAUpdater.cpp | 94 unsigned SrcReg = I->getOperand(i).getReg();
102 return I->getOperand(0).getReg();
152 return NewDef->getOperand(0).getReg();
204 return InsertedPHI->getOperand(0).getReg();
272 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
300 return NewDef->getOperand(0).getReg();
311 return PHI->getOperand(0).getReg();
347 return PHI->getOperand(0).getReg();
|
| MachineCopyPropagation.cpp | 115 unsigned SrcSrc = CopyMI->getOperand(1).getReg();
119 unsigned SrcDef = CopyMI->getOperand(0).getReg();
151 unsigned Def = MI->getOperand(0).getReg();
152 unsigned Src = MI->getOperand(1).getReg();
241 unsigned Reg = MO.getReg();
273 unsigned Reg = (*DI)->getOperand(0).getReg();
311 if (!MRI->isReserved((*DI)->getOperand(0).getReg())) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 57 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
69 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
113 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
125 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/form/ |
| Form11n.java | 72 unsignedFitsInNibble(regs.get(0).getReg()))) {
102 opcodeUnit(insn, makeByte(regs.get(0).getReg(), value & 0xf)));
|
| Form21s.java | 71 unsignedFitsInByte(regs.get(0).getReg()))) {
101 opcodeUnit(insn, regs.get(0).getReg()),
|
| Form31i.java | 71 unsignedFitsInByte(regs.get(0).getReg()))) {
99 opcodeUnit(insn, regs.get(0).getReg()),
|
| Form51l.java | 72 unsignedFitsInByte(regs.get(0).getReg()))) {
96 opcodeUnit(insn, regs.get(0).getReg()),
|
| /dalvik/dx/src/com/android/dx/dex/code/form/ |
| Form3rc.java | 92 unsignedFitsInShort(regs.get(0).getReg()) &&
101 int firstReg = (regs.size() == 0) ? 0 : regs.get(0).getReg();
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| InterferenceRegisterMapper.java | 108 return interferes(oldSpec.getReg(), newReg, oldSpec.getCategory());
147 int r = oldToNew(oldSpec.getReg());
|
| EscapeAnalysis.java | 128 if (e.regSet.get(reg.getReg())) {
231 escSet = new EscapeSet(result.getReg(), regCount, EscapeState.NONE);
237 escSet = new EscapeSet(result.getReg(), regCount, EscapeState.NONE);
262 escSet = new EscapeSet(result.getReg(), regCount,
271 escSet = new EscapeSet(result.getReg(), regCount,
276 escSet = new EscapeSet(result.getReg(), regCount,
282 escSet = new EscapeSet(result.getReg(), regCount,
295 escSet.regSet.set(result.getReg());
301 escSet = new EscapeSet(result.getReg(), regCount,
304 escSet = new EscapeSet(result.getReg(), regCount
[all...] |
| SsaMethod.java | 421 definitionList[insn.getResult().getReg()] = insn;
424 definitionList[phi.getResult().getReg()] = phi;
429 definitionList[insn.getResult().getReg()] = insn;
473 useList[rl.get(i).getReg()].add(insn);
498 int reg = oldSource.getReg();
502 int reg = newSource.getReg();
530 int reg = sources.get(i).getReg();
551 if (!useList[oldSources.get(i).getReg()].remove(insn)) {
581 definitionList[resultReg.getReg()] = null;
614 int reg = oldResult.getReg();
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/form/ |
| Form3rc.java | 92 unsignedFitsInShort(regs.get(0).getReg()) &&
101 int firstReg = (regs.size() == 0) ? 0 : regs.get(0).getReg();
|
| Form5rc.java | 91 unsignedFitsInShort(regs.get(0).getReg()) &&
100 int firstReg = (regs.size() == 0) ? 0 : regs.get(0).getReg();
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| InterferenceRegisterMapper.java | 110 return interferes(oldSpec.getReg(), newReg, oldSpec.getCategory());
149 int r = oldToNew(oldSpec.getReg());
|
| SsaInsn.java | 115 return result != null && result.getReg() == reg;
143 result.getReg(), result.getType(), local);
|
| EscapeAnalysis.java | 129 if (e.regSet.get(reg.getReg())) {
232 escSet = new EscapeSet(result.getReg(), regCount, EscapeState.NONE);
238 escSet = new EscapeSet(result.getReg(), regCount, EscapeState.NONE);
263 escSet = new EscapeSet(result.getReg(), regCount,
272 escSet = new EscapeSet(result.getReg(), regCount,
277 escSet = new EscapeSet(result.getReg(), regCount,
283 escSet = new EscapeSet(result.getReg(), regCount,
296 escSet.regSet.set(result.getReg());
302 escSet = new EscapeSet(result.getReg(), regCount,
305 escSet = new EscapeSet(result.getReg(), regCount
[all...] |
| SsaMethod.java | 422 definitionList[insn.getResult().getReg()] = insn;
425 definitionList[phi.getResult().getReg()] = phi;
430 definitionList[insn.getResult().getReg()] = insn;
474 useList[rl.get(i).getReg()].add(insn);
499 int reg = oldSource.getReg();
503 int reg = newSource.getReg();
531 int reg = sources.get(i).getReg();
552 if (!useList[oldSources.get(i).getReg()].remove(insn)) {
582 definitionList[resultReg.getReg()] = null;
615 int reg = oldResult.getReg();
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 123 I->getOperand(0).getReg()));
144 unsigned Reg = MI.getOperand(0).getReg();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 40 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
61 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
66 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
161 O << AArch64InstPrinter::getRegisterName(MO.getReg());
260 O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']';
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 324 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
346 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
357 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
376 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
388 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
399 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
410 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
423 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
424 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
445 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 263 unsigned Reg = MO.getReg();
273 unsigned Reg = MO.getReg();
346 unsigned Reg = MO.getReg();
386 if (MI->getOperand(1).getReg() == ARM::SP) {
420 unsigned BaseReg = MI->getOperand(0).getReg();
428 if (MI->getOperand(i).getReg() == BaseReg) {
442 unsigned BaseReg = MI->getOperand(1).getReg();
456 unsigned BaseReg = MI->getOperand(1).getReg();
476 OffsetReg = MI->getOperand(2).getReg();
535 if (MI->getOperand(1).getReg() != ARM::SP)
[all...] |
| ARMBaseInstrInfo.cpp | 157 unsigned WBReg = WB.getReg();
158 unsigned BaseReg = Base.getReg();
159 unsigned OffReg = Offset.getReg();
212 get(MemOpc), MI->getOperand(0).getReg())
216 get(MemOpc)).addReg(MI->getOperand(1).getReg())
223 get(MemOpc), MI->getOperand(0).getReg())
227 get(MemOpc)).addReg(MI->getOperand(1).getReg())
239 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
240 unsigned Reg = MO.getReg();
415 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
[all...] |
