| /dalvik/dx/src/com/android/dx/dex/code/form/ |
| Form22b.java | 73 unsignedFitsInByte(regs.get(0).getReg()) &&
74 unsignedFitsInByte(regs.get(1).getReg()))) {
96 bits.set(0, unsignedFitsInByte(regs.get(0).getReg()));
97 bits.set(1, unsignedFitsInByte(regs.get(1).getReg()));
109 opcodeUnit(insn, regs.get(0).getReg()),
110 codeUnit(regs.get(1).getReg(), value & 0xff));
|
| Form22c.java | 75 unsignedFitsInNibble(regs.get(0).getReg()) &&
76 unsignedFitsInNibble(regs.get(1).getReg()))) {
98 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg()));
99 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg()));
111 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form22s.java | 73 unsignedFitsInNibble(regs.get(0).getReg()) &&
74 unsignedFitsInNibble(regs.get(1).getReg()))) {
96 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg()));
97 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg()));
110 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form35c.java | 112 bits.set(i, unsignedFitsInNibble(reg.getReg() +
125 int r0 = (sz > 0) ? regs.get(0).getReg() : 0;
126 int r1 = (sz > 1) ? regs.get(1).getReg() : 0;
127 int r2 = (sz > 2) ? regs.get(2).getReg() : 0;
128 int r3 = (sz > 3) ? regs.get(3).getReg() : 0;
129 int r4 = (sz > 4) ? regs.get(4).getReg() : 0;
167 if (!unsignedFitsInNibble(one.getReg() + one.getCategory() - 1)) {
200 RegisterSpec.make(one.getReg() + 1, Type.VOID));
|
| Form11x.java | 68 unsignedFitsInByte(regs.get(0).getReg());
77 bits.set(0, unsignedFitsInByte(regs.get(0).getReg()));
85 write(out, opcodeUnit(insn, regs.get(0).getReg()));
|
| Form21t.java | 68 unsignedFitsInByte(regs.get(0).getReg()))) {
82 bits.set(0, unsignedFitsInByte(regs.get(0).getReg()));
102 opcodeUnit(insn, regs.get(0).getReg()),
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/form/ |
| Form22b.java | 74 unsignedFitsInByte(regs.get(0).getReg()) &&
75 unsignedFitsInByte(regs.get(1).getReg()))) {
97 bits.set(0, unsignedFitsInByte(regs.get(0).getReg()));
98 bits.set(1, unsignedFitsInByte(regs.get(1).getReg()));
110 opcodeUnit(insn, regs.get(0).getReg()),
111 codeUnit(regs.get(1).getReg(), value & 0xff));
|
| Form22c.java | 76 unsignedFitsInNibble(regs.get(0).getReg()) &&
77 unsignedFitsInNibble(regs.get(1).getReg()))) {
99 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg()));
100 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg()));
112 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form22s.java | 74 unsignedFitsInNibble(regs.get(0).getReg()) &&
75 unsignedFitsInNibble(regs.get(1).getReg()))) {
97 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg()));
98 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg()));
111 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form32s.java | 78 unsignedFitsInByte(regs.get(0).getReg()) &&
79 unsignedFitsInByte(regs.get(1).getReg()))) {
101 bits.set(0, unsignedFitsInByte(regs.get(0).getReg()));
102 bits.set(1, unsignedFitsInByte(regs.get(1).getReg()));
115 codeUnit(regs.get(0).getReg(), regs.get(1).getReg()),
|
| Form52c.java | 80 unsignedFitsInShort(regs.get(0).getReg()) &&
81 unsignedFitsInShort(regs.get(1).getReg()))) {
98 bits.set(0, unsignedFitsInShort(regs.get(0).getReg()));
99 bits.set(1, unsignedFitsInShort(regs.get(1).getReg()));
112 (short) regs.get(0).getReg(),
113 (short) regs.get(1).getReg());
|
| Form35c.java | 113 bits.set(i, unsignedFitsInNibble(reg.getReg() +
126 int r0 = (sz > 0) ? regs.get(0).getReg() : 0;
127 int r1 = (sz > 1) ? regs.get(1).getReg() : 0;
128 int r2 = (sz > 2) ? regs.get(2).getReg() : 0;
129 int r3 = (sz > 3) ? regs.get(3).getReg() : 0;
130 int r4 = (sz > 4) ? regs.get(4).getReg() : 0;
168 if (!unsignedFitsInNibble(one.getReg() + one.getCategory() - 1)) {
201 RegisterSpec.make(one.getReg() + 1, Type.VOID));
|
| Form11x.java | 69 unsignedFitsInByte(regs.get(0).getReg());
78 bits.set(0, unsignedFitsInByte(regs.get(0).getReg()));
86 write(out, opcodeUnit(insn, regs.get(0).getReg()));
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 113 printRegName(O, Dst.getReg());
115 printRegName(O, MO1.getReg());
118 printRegName(O, MO2.getReg());
135 printRegName(O, Dst.getReg());
137 printRegName(O, MO1.getReg());
155 MI->getOperand(0).getReg() == ARM::SP &&
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
172 printRegName(O, MI->getOperand(1).getReg());
180 MI->getOperand(0).getReg() == ARM::SP &&
192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/form/ |
| Form22b.java | 72 unsignedFitsInByte(regs.get(0).getReg()) &&
73 unsignedFitsInByte(regs.get(1).getReg()))) {
103 opcodeUnit(insn, regs.get(0).getReg()),
104 codeUnit(regs.get(1).getReg(), value & 0xff));
|
| Form22c.java | 75 unsignedFitsInNibble(regs.get(0).getReg()) &&
76 unsignedFitsInNibble(regs.get(1).getReg()))) {
106 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form22s.java | 72 unsignedFitsInNibble(regs.get(0).getReg()) &&
73 unsignedFitsInNibble(regs.get(1).getReg()))) {
104 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form22t.java | 68 unsignedFitsInNibble(regs.get(0).getReg()) &&
69 unsignedFitsInNibble(regs.get(1).getReg()))) {
100 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
|
| Form31c.java | 90 if (reg.getReg() != regs.get(1).getReg()) {
100 if (!unsignedFitsInByte(reg.getReg())) {
125 opcodeUnit(insn, regs.get(0).getReg()),
|
| Form35c.java | 108 int r0 = (sz > 0) ? regs.get(0).getReg() : 0;
109 int r1 = (sz > 1) ? regs.get(1).getReg() : 0;
110 int r2 = (sz > 2) ? regs.get(2).getReg() : 0;
111 int r3 = (sz > 3) ? regs.get(3).getReg() : 0;
112 int r4 = (sz > 4) ? regs.get(4).getReg() : 0;
150 if (!unsignedFitsInNibble(one.getReg() + one.getCategory() - 1)) {
183 RegisterSpec.make(one.getReg() + 1, Type.VOID));
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 50 O << getRegisterName(Op.getReg());
73 if (!Base.getReg())
84 if (Base.getReg())
85 O << '(' << getRegisterName(Base.getReg()) << ')';
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 102 TII->getIndirectAddrStoreRegClass(MI.getOperand(0).getReg());
104 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
116 MI.getOperand(0).getReg(), // Value
118 MI.getOperand(1).getReg()); // Offset
224 RegisterAddressMap.find(MO.getReg()) != RegisterAddressMap.end()) {
225 unsigned Reg = MO.getReg();
252 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
264 MI.getOperand(0).getReg())
271 MI.getOperand(0).getReg())
304 MI.getOperand(0).getReg(), // Valu
[all...] |
| R600ExpandSpecialInstrs.cpp | 80 MI.getOperand(0).getReg(), // dst
81 MI.getOperand(1).getReg(), // src0
102 DstReg = MI.getOperand(Chan).getReg();
107 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
133 DstReg = MI.getOperand(Chan-2).getReg();
136 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
156 unsigned DstReg = MI.getOperand(0).getReg();
175 unsigned DstReg = MI.getOperand(0).getReg();
197 .getReg();
200 .getReg();
[all...] |
| /external/llvm/lib/CodeGen/ |
| OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg();
99 unsigned SrcReg = MI->getOperand(i).getReg();
108 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
130 unsigned DstReg = MI->getOperand(0).getReg();
167 unsigned OldReg = MI->getOperand(0).getReg();
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 143 printRegName(O, Op.getReg());
161 if (SegReg.getReg()) {
169 if (BaseReg.getReg()) {
174 if (IndexReg.getReg()) {
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
