| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 170 .addReg(MII->getOperand(1).getReg());
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 344 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
345 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
346 Candidates.reset(MO.getReg());
362 DefReg = MO.getReg();
|
| MipsMCInstLower.cpp | 138 return MCOperand::CreateReg(MO.getReg());
|
| MipsSEISelDAGToDAG.cpp | 75 (MI.getOperand(1).getReg() == Mips::ZERO) &&
77 DstReg = MI.getOperand(0).getReg();
80 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
82 DstReg = MI.getOperand(0).getReg();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 164 unsigned CRReg = I->getOperand(1).getReg();
|
| PPCFrameLowering.cpp | 122 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
124 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
136 unsigned SrcReg = MI->getOperand(1).getReg();
137 unsigned DstReg = MI->getOperand(0).getReg();
315 switch (MO.getReg()) {
657 unsigned Reg = CSI[I].getReg();
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 173 return MRI.getEncodingValue(MO.getReg());
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 105 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
|
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 145 if (isYmmReg(MO.getReg()))
|
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| ARMFrameLowering.cpp | 104 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
111 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
112 MI->getOperand(1).getReg() == ARM::SP)
175 unsigned Reg = CSI[i].getReg();
464 addReg(JumpTarget.getReg(), RegState::Kill);
597 unsigned Reg = CSI[i-1].getReg();
668 unsigned Reg = CSI[i-1].getReg();
745 unsigned DNum = CSI[i].getReg() - ARM::D8;
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| RegisterSpec.java | 321 public int getReg() {
437 if ((other == null) || (reg != other.getReg())) {
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| InsnFormat.java | 444 int first = list.get(0).getReg();
449 if (one.getReg() != next) {
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| RegisterSpec.java | 325 public int getReg() {
441 if ((other == null) || (reg != other.getReg())) {
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| InsnFormat.java | 445 int first = list.get(0).getReg();
450 if (one.getReg() != next) {
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| RegisterSpec.java | 326 public int getReg() {
442 if ((other == null) || (reg != other.getReg())) {
|
| /external/llvm/lib/CodeGen/ |
| ScheduleDAGInstrs.cpp | 216 unsigned Reg = MO.getReg();
251 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
298 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
326 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
330 unsigned Reg = MO.getReg();
368 unsigned Reg = MI->getOperand(OperIdx).getReg();
406 unsigned Reg = MI->getOperand(OperIdx).getReg();
757 unsigned Reg = MO.getReg();
[all...] |
| VirtRegMap.cpp | 284 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
286 unsigned VirtReg = MO.getReg();
|
| LiveIntervalAnalysis.cpp | 749 unsigned Reg = MO->getReg();
[all...] |
| MachineBasicBlock.cpp | 361 if (I->getOperand(1).getReg() == PhysReg) {
362 unsigned VirtReg = I->getOperand(0).getReg();
725 if (!OI->isReg() || OI->getReg() == 0 ||
728 unsigned Reg = OI->getReg();
746 if (!OI->isReg() || OI->getReg() == 0)
749 unsigned Reg = OI->getReg();
856 unsigned Reg = MO.getReg();
[all...] |
| MachineTraceMetrics.cpp | 646 unsigned Reg = MO->getReg();
673 unsigned Reg = UseMI->getOperand(i).getReg();
709 unsigned Reg = MO->getReg();
741 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 196 unsigned Reg = CSI[i-1].getReg();
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
|
| /external/llvm/lib/Target/R600/ |
| SIInsertWaits.cpp | 142 unsigned Reg = Op.getReg();
187 unsigned Reg = Op.getReg();
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 117 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
635 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
772 if (II->getReg()) {
773 Reg = II->getReg();
781 assert(I->getReg() && "Unknown physical register!");
787 .addReg(I->getReg());
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfCompileUnit.cpp | 401 addRegisterOp(Block, Location.getReg());
403 addRegisterOffset(Block, Location.getReg(), Location.getOffset());
428 addRegisterOffset(Block, Location.getReg(), DV.getAddrElement(1));
431 addRegisterOp(Block, Location.getReg());
434 addRegisterOffset(Block, Location.getReg(), Location.getOffset());
556 addRegisterOp(Block, Location.getReg());
558 addRegisterOffset(Block, Location.getReg(), Location.getOffset());
[all...] |
