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    Searched refs:isReg (Results 51 - 75 of 163) sorted by null

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  /external/llvm/lib/Target/X86/
X86MCInstLower.cpp 239 assert(Inst.getOperand(0).isReg() &&
241 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
293 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
297 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
298 Inst.getOperand(AddrBase + 0).isReg() && // base
300 Inst.getOperand(AddrBase + 2).isReg() && // index register
303 Inst.getOperand(AddrBase + 4).isReg() && // segment
X86VZeroUpper.cpp 141 if (!MO.isReg())
  /external/llvm/utils/TableGen/
CodeGenInstruction.h 312 bool isReg() const { return Kind == K_Reg; }
317 Record *getRegister() const { assert(isReg()); return R; }
  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp 143 if (MO.isReg()) {
235 if (MO.isReg()) {
R600MCCodeEmitter.cpp 245 if (MO.isReg()) {
264 if (MO.isReg()) {
273 (MO.isReg() &&
301 if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
623 if (MO.isReg()) {
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
R600MCCodeEmitter.cpp 245 if (MO.isReg()) {
264 if (MO.isReg()) {
273 (MO.isReg() &&
301 if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
623 if (MO.isReg()) {
  /external/llvm/lib/CodeGen/
CriticalAntiDepBreaker.cpp 171 if (!MO.isReg()) continue;
234 if (!MO.isReg()) continue;
265 if (!MO.isReg()) continue;
335 if (!CheckOper.isReg() || !CheckOper.isDef() ||
578 if (!MO.isReg()) continue;
ExecutionDepsFix.cpp 460 if (!MO.isReg())
514 if (!mo.isReg()) continue;
523 if (!mo.isReg()) continue;
543 if (!mo.isReg()) continue;
635 if (!mo.isReg()) continue;
TwoAddressInstructionPass.cpp 195 if (!MO.isReg())
268 if (!MO.isReg())
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
802 if (!MO.isReg())
845 if (!MO.isReg())
    [all...]
AggressiveAntiDepBreaker.cpp 226 if (!MO.isReg() || !MO.isImplicit())
246 if (!MO.isReg()) continue;
348 if (!MO.isReg() || !MO.isDef()) continue;
358 if (!MO.isReg() || !MO.isDef()) continue;
398 if (!MO.isReg() || !MO.isDef()) continue;
441 if (!MO.isReg() || !MO.isUse()) continue;
476 if (!MO.isReg()) continue;
    [all...]
LiveRangeEdit.cpp 84 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
249 if (!MOI->isReg())
302 if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
PeepholeOptimizer.cpp 322 if (!MO.isReg())
349 if (!MO.isReg() || MO.isDef())
464 if (!MO.isReg() || MO.isDef())
Spiller.cpp 111 if (!op.isReg() || op.getReg() != li->reg)
  /external/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 261 if (!MO.isReg() || MO.isUndef() || MO.isUse())
271 if (!MO.isReg() || MO.isUndef() || MO.isDef())
344 if (!MO.isReg() || MO.isImplicit())
769 if (MO.isReg()) {
840 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
863 if (!MO.isReg() || MO.isUndef() || MO.isUse())
879 if (!MO.isReg() || MO.isUndef() || MO.isDef())
    [all...]
ARMAsmPrinter.cpp 224 assert(MLoc.isReg() && !Indirect &&
418 if (MI->getOperand(OpNum).isReg()) {
435 if (MI->getOperand(OpNum).isReg()) {
460 if (!MI->getOperand(OpNum).isReg())
481 while (MI->getOperand(RegOps).isReg()) {
506 if (!MO.isReg())
520 if (!MO.isReg())
529 if (!MI->getOperand(OpNum).isReg())
546 if (!MO.isReg())
576 if (!MI->getOperand(OpNum).isReg())
    [all...]
  /external/llvm/lib/Target/Mips/
MipsAsmPrinter.cpp 389 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
414 if (!MO.isReg())
442 assert(MO.isReg() && "unexpected inline asm memory operand");
  /external/llvm/lib/Target/R600/
R600MachineScheduler.cpp 181 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
224 if (I->isReg() && I->getReg() == AMDGPU::AR_X) {
391 if (MO.isReg() && !MO.isDef() &&
AMDGPUInstrInfo.cpp 235 if (MO.isReg() && MO.isDef()) {
  /external/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 112 MI->getOperand(0).isReg() &&
144 if (MO.isReg()) {
383 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ?
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUInstrInfo.cpp 247 if (MO.isReg() && MO.isDef()) {
  /external/llvm/lib/Target/Hexagon/
HexagonFixupHwLoops.cpp 167 if (MII->getOperand(1).isReg()) {
  /external/llvm/lib/Target/R600/MCTargetDesc/
R600MCCodeEmitter.cpp 173 if (MO.isReg()) {
SIMCCodeEmitter.cpp 172 if (MO.isReg())
  /external/llvm/lib/Target/X86/InstPrinter/
X86IntelInstPrinter.cpp 142 if (Op.isReg()) {
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUInstrInfo.cpp 247 if (MO.isReg() && MO.isDef()) {

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