| /external/qemu/ |
| cache-utils.c | 47 unsigned cacheline; local
50 len = sizeof(cacheline);
51 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
54 qemu_cache_conf.dcache_bsize = cacheline;
55 qemu_cache_conf.icache_bsize = cacheline;
71 unsigned cacheline; local
73 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
79 qemu_cache_conf.dcache_bsize = cacheline;
80 qemu_cache_conf.icache_bsize = cacheline;
|
| /external/kernel-headers/original/asm-x86/ |
| cache.h | 11 /* vSMP Internode cacheline shift */
|
| segment_32.h | 12 * 4 - unused <==== new cacheline
26 * 12 - kernel code segment <==== new cacheline
|
| /external/kernel-headers/original/linux/ |
| cache.h | 47 * These could be inter-node cacheline sizes/L3 cacheline
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/util/ |
| u_cpu_detect.c | 258 util_cpu_caps.cacheline = 32;
264 unsigned int cacheline; local
284 cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
285 if (cacheline > 0)
286 util_cpu_caps.cacheline = cacheline;
303 util_cpu_caps.cacheline = regs2[2] & 0xFF;
324 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
|
| u_cpu_detect.h | 53 unsigned cacheline; member in struct:util_cpu_caps
|
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_cpu_detect.c | 258 util_cpu_caps.cacheline = 32;
264 unsigned int cacheline; local
284 cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
285 if (cacheline > 0)
286 util_cpu_caps.cacheline = cacheline;
303 util_cpu_caps.cacheline = regs2[2] & 0xFF;
324 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
|
| u_cpu_detect.h | 53 unsigned cacheline; member in struct:util_cpu_caps
|
| /external/oprofile/events/arm/armv6/ |
| events.h | 25 "data cache writeback, 1 event for every half cacheline"},
|
| events | 14 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/ |
| system-alloc.h | 56 // CACHELINE_ALIGNED, the return pointer will always be cacheline
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/ |
| system-alloc.h | 56 // CACHELINE_ALIGNED, the return pointer will always be cacheline
|
| /external/oprofile/events/arm/xscale1/ |
| events | 15 event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/oprofile/events/arm/xscale2/ |
| events | 15 event:0x0c counters:1,2,3,4 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/stressapptest/ |
| stressapptest.1 | 85 Number of times to increment the cacheline's member.
|
| /external/stressapptest/src/ |
| os.h | 113 // Flushes cacheline. Used to distinguish read or write errors.
115 // Takes a pointer, and flushed the cacheline containing that pointer.
|
| worker.h | 362 // Report a mistagged cacheline.
648 cc_cacheline_data *cc_cacheline_data_; // Datstructure for each cacheline.
653 // of the cacheline datastructure.
|
| /external/valgrind/main/helgrind/ |
| libhb_core.c | 87 # define CHECK_ZSM 1 /* do sanity-check CacheLine stuff */
91 # define CHECK_ZSM 0 /* don't sanity-check CacheLine stuff */
422 /* ------ CacheLine ------ */
433 CacheLine;
473 CacheLine-sized chunks of SecMaps are copied into a Cache, being
529 /* Each tag is the address of the associated CacheLine, rounded down
530 to a CacheLine address boundary. A CacheLine size must be a power
538 CacheLine lyns0[N_WAY_NENT];
545 a CacheLine. *
[all...] |
| /external/kernel-headers/original/asm-generic/bitops/ |
| atomic.h | 15 * Since "a" is usually an address, use one spinlock per cacheline.
|
| /bionic/libc/arch-arm/bionic/ |
| memcpy.a15.S | 106 than loads that cross cacheline boundary.
122 /* TODO: Align to cacheline (useful for PLD optimization). */
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 194 // TODO: Make the loads schedule near if it fits in a cacheline
|
| /external/kernel-headers/original/linux/netfilter_ipv4/ |
| ip_conntrack.h | 127 /* Traversed often, so hopefully in different cacheline to top */
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.cpp | 174 // TODO: Make the loads schedule near if it fits in a cacheline
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 194 // TODO: Make the loads schedule near if it fits in a cacheline
|
| /prebuilts/gcc/darwin-x86/host/i686-apple-darwin-4.2.1/include/gcc/darwin/4.2/ |
| ppc_intrinsics.h | 312 * cacheline is
316 * of the cacheline to be operated on.
318 * Effective Address of cacheline to be manipulated =
|
