| /external/valgrind/main/none/tests/x86/ |
| cpuid.vgtest | 1 prog: cpuid
|
| cpuid.stdout.exp | 0 cpuid words (0): 0x........ 0x........ 0x........ 0x........
2 cpuid words (1): 0x........ 0x........ 0x........ 0x........
|
| cpuid_c.c | 13 printf("cpuid words (0): 0x%x 0x%x 0x%x 0x%x\n",
17 printf("cpuid words (1): 0x%x 0x%x 0x%x 0x%x\n",
|
| /external/valgrind/main/VEX/useful/ |
| cpuid.c | 7 void cpuid ( UInt* eax, UInt* ebx, UInt* ecx, UInt* edx, function
11 asm volatile ("cpuid"
25 cpuid(&eax,&ebx,&ecx,&edx, 0,0);
29 cpuid(&eax,&ebx,&ecx,&edx, i,0);
34 cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in);
42 cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in);
50 cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in);
60 cpuid(&eax,&ebx,&ecx,&edx, 0x80000000,0);
63 cpuid(&eax,&ebx,&ecx,&edx, i,0);
67 cpuid(&eax,&ebx,&ecx,&edx, 1234,0)
79 void cpuid ( UInt* eax, UInt* ebx, UInt* ecx, UInt* edx, function
[all...] |
| /external/oprofile/events/i386/arch_perfmon/ |
| events | 4 event:0x3c counters:cpuid um:zero minimum:6000 filter:0 name:CPU_CLK_UNHALTED : Clock cycles when not halted
5 event:0x3c counters:cpuid um:one minimum:6000 filter:2 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
6 event:0xc0 counters:cpuid um:zero minimum:6000 filter:1 name:INST_RETIRED : number of instructions retired
7 event:0x2e counters:cpuid um:x41 minimum:6000 filter:4 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
8 event:0x2e counters:cpuid um:x4f minimum:6000 filter:3 name:LLC_REFS : Last level cache demand requests from this core
9 event:0xc4 counters:cpuid um:zero minimum:500 filter:5 name:BR_INST_RETIRED : number of branch instructions retired
10 event:0xc5 counters:cpuid um:zero minimum:500 filter:6 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
|
| /prebuilts/gcc/darwin-x86/x86/i686-linux-android-4.6/lib/gcc/i686-linux-android/4.6/include/ |
| cpuid.h | 74 "cpuid\n\t" \
81 "cpuid\n\t" \
90 "cpuid\n\t" \
97 "cpuid\n\t" \
104 __asm__ ("cpuid\n\t" \
109 __asm__ ("cpuid\n\t" \
114 /* Return highest supported input value for cpuid instruction. ext can
116 basic or extended cpuid information. Function returns 0 if cpuid
117 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /prebuilts/gcc/darwin-x86/x86/i686-linux-android-4.7/lib/gcc/i686-linux-android/4.7/include/ |
| cpuid.h | 77 "cpuid\n\t" \
84 "cpuid\n\t" \
93 "cpuid\n\t" \
100 "cpuid\n\t" \
107 __asm__ ("cpuid\n\t" \
112 __asm__ ("cpuid\n\t" \
117 /* Return highest supported input value for cpuid instruction. ext can
119 basic or extended cpuid information. Function returns 0 if cpuid
120 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/lib/gcc/i686-linux/4.4.3/include/ |
| cpuid.h | 65 "cpuid\n\t" \
72 "cpuid\n\t" \
81 "cpuid\n\t" \
88 "cpuid\n\t" \
95 __asm__ ("cpuid\n\t" \
100 __asm__ ("cpuid\n\t" \
105 /* Return highest supported input value for cpuid instruction. ext can
107 basic or extended cpuid information. Function returns 0 if cpuid
108 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/lib/gcc/i686-linux/4.6.x-google/include/ |
| cpuid.h | 74 "cpuid\n\t" \
81 "cpuid\n\t" \
90 "cpuid\n\t" \
97 "cpuid\n\t" \
104 __asm__ ("cpuid\n\t" \
109 __asm__ ("cpuid\n\t" \
114 /* Return highest supported input value for cpuid instruction. ext can
116 basic or extended cpuid information. Function returns 0 if cpuid
117 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/lib/gcc/x86_64-linux/4.6.x-google/include/ |
| cpuid.h | 74 "cpuid\n\t" \
81 "cpuid\n\t" \
90 "cpuid\n\t" \
97 "cpuid\n\t" \
104 __asm__ ("cpuid\n\t" \
109 __asm__ ("cpuid\n\t" \
114 /* Return highest supported input value for cpuid instruction. ext can
116 basic or extended cpuid information. Function returns 0 if cpuid
117 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /prebuilts/gcc/linux-x86/x86/i686-linux-android-4.6/lib/gcc/i686-linux-android/4.6/include/ |
| cpuid.h | 74 "cpuid\n\t" \
81 "cpuid\n\t" \
90 "cpuid\n\t" \
97 "cpuid\n\t" \
104 __asm__ ("cpuid\n\t" \
109 __asm__ ("cpuid\n\t" \
114 /* Return highest supported input value for cpuid instruction. ext can
116 basic or extended cpuid information. Function returns 0 if cpuid
117 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/lib/gcc/i686-linux-android/4.7/include/ |
| cpuid.h | 77 "cpuid\n\t" \
84 "cpuid\n\t" \
93 "cpuid\n\t" \
100 "cpuid\n\t" \
107 __asm__ ("cpuid\n\t" \
112 __asm__ ("cpuid\n\t" \
117 /* Return highest supported input value for cpuid instruction. ext can
119 basic or extended cpuid information. Function returns 0 if cpuid
120 is not supported or whatever cpuid returns in eax register. If si
[all...] |
| /external/chromium/base/ |
| atomicops_internals_x86_gcc.cc | 19 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
21 // must preserve that register's value across cpuid instructions.
23 #define cpuid(a, b, c, d, inp) \ macro
25 "cpuid\n" \
29 #define cpuid(a, b, c, d, inp) \ macro
31 "cpuid\n" \
36 #if defined(cpuid) // initialize the struct only on x86
53 // Get vendor string (issue CPUID with eax = 0)
54 cpuid(eax, ebx, ecx, edx, 0);
62 cpuid(eax, ebx, ecx, edx, 1)
[all...] |
| /external/chromium_org/base/ |
| atomicops_internals_x86_gcc.cc | 19 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
21 // must preserve that register's value across cpuid instructions.
23 #define cpuid(a, b, c, d, inp) \ macro
25 "cpuid\n" \
29 #define cpuid(a, b, c, d, inp) \ macro
31 "cpuid\n" \
36 #if defined(cpuid) // initialize the struct only on x86
53 // Get vendor string (issue CPUID with eax = 0)
54 cpuid(eax, ebx, ecx, edx, 0);
62 cpuid(eax, ebx, ecx, edx, 1)
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| msr.h | 74 static __inline__ void cpuid(int op, unsigned int *eax, unsigned int *ebx, function
77 __asm__("cpuid"
85 /* Some CPUID calls want 'count' to be placed in ecx */
89 __asm__("cpuid"
98 * CPUID functions returning a single datum
104 __asm__("cpuid"
114 __asm__("cpuid"
124 __asm__("cpuid"
134 __asm__("cpuid"
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| msr.h | 74 static __inline__ void cpuid(int op, unsigned int *eax, unsigned int *ebx, function
77 __asm__("cpuid"
85 /* Some CPUID calls want 'count' to be placed in ecx */
89 __asm__("cpuid"
98 * CPUID functions returning a single datum
104 __asm__("cpuid"
114 __asm__("cpuid"
124 __asm__("cpuid"
134 __asm__("cpuid"
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| msr.h | 74 static __inline__ void cpuid(int op, unsigned int *eax, unsigned int *ebx, function
77 __asm__("cpuid"
85 /* Some CPUID calls want 'count' to be placed in ecx */
89 __asm__("cpuid"
98 * CPUID functions returning a single datum
104 __asm__("cpuid"
114 __asm__("cpuid"
124 __asm__("cpuid"
134 __asm__("cpuid"
|
| /external/libvpx/libvpx/vpx_ports/ |
| x86.h | 38 #define cpuid(func,ax,bx,cx,dx)\ macro
40 "cpuid \n\t" \
44 #define cpuid(func,ax,bx,cx,dx)\ macro
47 "cpuid \n\t" \
54 #define cpuid(func,ax,bx,cx,dx)\ macro
57 "cpuid \n\t" \
63 #define cpuid(func,ax,bx,cx,dx)\ macro
66 "cpuid \n\t" \
76 #define cpuid(func,a,b,c,d) do{\ macro
81 #define cpuid(func,a,b,c,d) macro
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| common_x86_asm.S | 26 * Check extended CPU capabilities. Now justs returns the raw CPUID
53 /* Test for the CPUID command. If the ID Flag bit in EFLAGS
54 * (bit 21) is writable, the CPUID command is present */
77 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
81 CPUID
101 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
104 CPUID
114 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
117 CPUID
128 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op *
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| common_x86_asm.S | 26 * Check extended CPU capabilities. Now justs returns the raw CPUID
53 /* Test for the CPUID command. If the ID Flag bit in EFLAGS
54 * (bit 21) is writable, the CPUID command is present */
77 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
81 CPUID
101 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
104 CPUID
114 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
117 CPUID
128 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op *
[all...] |
| /external/oprofile/libop/ |
| op_hw_specific.h | 26 "cpuid\n"
36 asm("cpuid" : "=a" (eax), "=b" (v.b), "=c" (v.c), "=d" (v.d) : "0" (0));
47 "cpuid\n"
54 asm("cpuid" : "=a" (v.eax) : "a" (code) : "ecx","ebx","edx");
84 /* Work around Nehalem spec update AAJ79: CPUID incorrectly indicates
86 steppings after C0 report correct data in CPUID. */
107 "cpuid\n"
115 asm("cpuid" : "=a" (eax), "=b" (ebx) : "0" (0xa) : "ecx","edx");
|
| /external/qemu/distrib/sdl-1.2.15/src/cpuinfo/ |
| SDL_cpuinfo.c | 71 " movl $1,%0 # We have CPUID support \n"
79 CPUid by definition. But it's nice to be able to prove it. :) */
91 " movl $1,%0 # We have CPUID support \n"
109 mov has_CPUID,1 ; We have CPUID support
151 " xorl %%eax,%%eax # Set up for CPUID instruction \n"
153 " cpuid # Get and save vendor ID \n"
155 " cmpl $1,%%eax # Make sure 1 is valid input for CPUID\n"
156 " jl 1f # We dont have the CPUID instruction\n"
160 " cpuid # Get family/model/stepping/features\n"
170 " xorl %%eax,%%eax # Set up for CPUID instruction \n
191 cpuid ; Get and save vendor ID local
198 cpuid ; Get family\/model\/stepping\/features local
[all...] |
| /external/chromium_org/third_party/protobuf/src/google/protobuf/stubs/ |
| atomicops_internals_x86_gcc.cc | 44 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
46 // must preserve that register's value across cpuid instructions.
48 #define cpuid(a, b, c, d, inp) \ macro
50 "cpuid\n" \
54 #define cpuid(a, b, c, d, inp) \ macro
56 "cpuid\n" \
61 #if defined(cpuid) // initialize the struct only on x86
84 // Get vendor string (issue CPUID with eax = 0)
85 cpuid(eax, ebx, ecx, edx, 0);
93 cpuid(eax, ebx, ecx, edx, 1)
[all...] |
| /external/chromium_org/third_party/tcmalloc/chromium/src/base/ |
| atomicops-internals-x86.cc | 47 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
49 // must preserve that register's value across cpuid instructions.
51 #define cpuid(a, b, c, d, inp) \ macro
53 "cpuid\n" \
57 #define cpuid(a, b, c, d, inp) \ macro
59 "cpuid\n" \
64 #if defined(cpuid) // initialize the struct only on x86
81 // Get vendor string (issue CPUID with eax = 0)
82 cpuid(eax, ebx, ecx, edx, 0);
90 cpuid(eax, ebx, ecx, edx, 1)
[all...] |
| /external/chromium_org/third_party/tcmalloc/vendor/src/base/ |
| atomicops-internals-x86.cc | 47 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
49 // must preserve that register's value across cpuid instructions.
51 #define cpuid(a, b, c, d, inp) \ macro
53 "cpuid\n" \
57 #define cpuid(a, b, c, d, inp) \ macro
59 "cpuid\n" \
64 #if defined(cpuid) // initialize the struct only on x86
81 // Get vendor string (issue CPUID with eax = 0)
82 cpuid(eax, ebx, ecx, edx, 0);
90 cpuid(eax, ebx, ecx, edx, 1)
[all...] |
