| /external/kernel-headers/original/asm-mips/ |
| fpregdef.h | 56 #define fcr31 $31 /* FPU status register */ macro
95 #define fcr31 $31 macro
|
| processor.h | 92 unsigned int fcr31; member in struct:mips_fpu_struct
182 .fcr31 = 0, \
|
| /bionic/libc/kernel/arch-mips/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| fpregdef.h | 64 #define fcr31 $31 macro
107 #define fcr31 $31 macro
|
| processor.h | 41 unsigned int fcr31; member in struct:mips_fpu_struct
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /external/qemu/target-mips/ |
| op_helper.c | [all...] |
| cpu.h | 87 uint32_t fcr31; member in struct:CPUMIPSFPUContext
88 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
90 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
|
| machine.c | 40 qemu_put_be32s(f, &fpu->fcr31);
187 qemu_get_be32s(f, &fpu->fcr31);
|
| translate.c | [all...] |
| /external/qemu/ |
| gdbstub.c | 993 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1015 /* convert MIPS rounding mode in FCR31 to IEEE library */
1024 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1046 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1051 SET_FP_ENABLE(env->active_fpu.fcr31, 0);
[all...] |
