| /external/eigen/Eigen/src/Core/arch/ |
| CMakeLists.txt | 3 ADD_SUBDIRECTORY(NEON)
|
| /ndk/tests/build/b9193874-neon/jni/ |
| Android.mk | 4 LOCAL_MODULE := b9193874-neon
5 LOCAL_SRC_FILES := b9193874-neon.c.neon
|
| /external/eigen/Eigen/src/Core/arch/NEON/ |
| CMakeLists.txt | 5 DESTINATION ${INCLUDE_INSTALL_DIR}/Eigen/src/Core/arch/NEON COMPONENT Devel
|
| /ndk/tests/build/stlport-src-suffix/ |
| README | 1 This test is meant to test STLport at the presence of .arm and/or .neon suffix
|
| /external/llvm/test/CodeGen/Thumb2/ |
| aligned-spill.ll | 1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
23 ; NEON: f
24 ; NEON: push {r4, r7, lr}
25 ; NEON: sub.w r4, sp, #64
26 ; NEON: bic r4, r4, #15
28 ; NEON: mov sp, r4
29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
30 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128
[all...] |
| /external/pixman/pixman/ |
| pixman-arm-neon.c | 37 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_8888_8888,
39 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_x888_8888,
41 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_0565_0565,
43 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_0888_0888,
45 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_8888_0565,
47 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_0565_8888,
49 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_0888_8888_rev,
51 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_0888_0565_rev,
53 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_pixbuf_8888,
55 PIXMAN_ARM_BIND_FAST_PATH_SRC_DST (neon, src_rpixbuf_8888
[all...] |
| /external/scrypt/patches/ |
| README | 9 arm-neon.patch:
11 Adds NEON acceleration for the Salsa20/8 mixing function.
|
| /ndk/tests/build/issue34613-neon/jni/ |
| Android.mk | 5 LOCAL_MODULE := issue34613-neon
7 LOCAL_SRC_FILES := issue34613-neon.cpp
|
| /external/llvm/test/CodeGen/ARM/ |
| fp_convert.ll | 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2
4 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NEON
5 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
11 ; NEON-LABEL: test1:
12 ; NEON: vadd.f32 [[D0:d[0-9]+]]
13 ; NEON: vcvt.s32.f32 d0, [[D0]]
23 ; NEON-LABEL: test2:
24 ; NEON: vadd.f32 [[D0:d[0-9]+]]
25 ; NEON: vcvt.u32.f32 d0, [[D0]]
35 ; NEON-LABEL: test3
[all...] |
| fmscs.ll | 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
10 ; NEON-LABEL: t1:
11 ; NEON: vnmls.f32
26 ; NEON-LABEL: t2:
27 ; NEON: vnmls.f64
|
| fnmacs.ll | 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
10 ; NEON-LABEL: t1:
11 ; NEON: vmls.f32
26 ; NEON-LABEL: t2:
27 ; NEON: vmls.f64
|
| vabs.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
15 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
23 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
31 %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
39 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
47 %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
55 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
63 %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
67 declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnon
[all...] |
| vqshrn.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
15 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
23 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
31 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
39 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
47 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
55 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
63 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
71 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >
[all...] |
| vshrn.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
15 %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
23 %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
27 declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
28 declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
29 declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
35 %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
43 %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
51 %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >
[all...] |
| vld1.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
2 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
16 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
26 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
36 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
46 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
56 %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
64 %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
72 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8
[all...] |
| /ndk/docs/text/ |
| CPU-ARM-NEON.text | 1 Android NDK & ARM NEON instruction set extension support
22 "NEON". It provides:
31 Not all ARMv7-based Android devices will support NEON, but those that
35 files with support for NEON. What this means is that a specific compiler
36 flag will be used to enable the use of GCC ARM Neon intrinsics and
39 > http://gcc.gnu.org/onlinedocs/gcc/ARM-NEON-Intrinsics.html
46 will build all its source files with NEON support. This can be useful if
48 NEON code paths.
51 Using the .neon suffix:
55 the option of using the .neon suffix to indicate that you want t
[all...] |
| /external/libvpx/ |
| Android.mk | 5 # if ARMv7 + NEON etc blah blah
|
| /external/libvpx/armv7a-neon/ |
| libvpx_srcs.txt | 33 vp8/common/arm/neon/bilinearpredict16x16_neon.asm.s
34 vp8/common/arm/neon/bilinearpredict4x4_neon.asm.s
35 vp8/common/arm/neon/bilinearpredict8x4_neon.asm.s
36 vp8/common/arm/neon/bilinearpredict8x8_neon.asm.s
37 vp8/common/arm/neon/buildintrapredictorsmby_neon.asm.s
38 vp8/common/arm/neon/copymem16x16_neon.asm.s
39 vp8/common/arm/neon/copymem8x4_neon.asm.s
40 vp8/common/arm/neon/copymem8x8_neon.asm.s
41 vp8/common/arm/neon/dc_only_idct_add_neon.asm.s
42 vp8/common/arm/neon/dequant_idct_neon.asm.
[all...] |
| /external/libvpx/libvpx/vpx_scale/ |
| vpx_scale.mk | 12 #neon
13 SCALE_SRCS-$(HAVE_NEON) += arm/neon/vp8_vpxyv12_copyframe_func_neon$(ASM)
14 SCALE_SRCS-$(HAVE_NEON) += arm/neon/vp8_vpxyv12_copy_y_neon$(ASM)
15 SCALE_SRCS-$(HAVE_NEON) += arm/neon/vp8_vpxyv12_copysrcframe_func_neon$(ASM)
16 SCALE_SRCS-$(HAVE_NEON) += arm/neon/vp8_vpxyv12_extendframeborders_neon$(ASM)
17 SCALE_SRCS-$(HAVE_NEON) += arm/neon/yv12extend_arm.c
|
| /external/chromium_org/third_party/skia/src/core/ |
| SkUtilsArm.h | 16 // - No ARM Neon support at all (not targetting ARMv7-A, or don't have NEON)
17 // - Full ARM Neon support (i.e. assume the CPU always supports it)
18 // - Optional ARM Neon support (i.e. probe CPU at runtime)
38 // is ARMv7-A and supports Neon instructions. In DYNAMIC mode, this actually
54 // Use SK_ARM_NEON_WRAP(symbol) to map 'symbol' to a NEON-specific symbol
56 // the current NEON configuration, i.e.:
|
| /external/skia/src/core/ |
| SkUtilsArm.h | 16 // - No ARM Neon support at all (not targetting ARMv7-A, or don't have NEON)
17 // - Full ARM Neon support (i.e. assume the CPU always supports it)
18 // - Optional ARM Neon support (i.e. probe CPU at runtime)
38 // is ARMv7-A and supports Neon instructions. In DYNAMIC mode, this actually
54 // Use SK_ARM_NEON_WRAP(symbol) to map 'symbol' to a NEON-specific symbol
56 // the current NEON configuration, i.e.:
|
| /external/llvm/test/CodeGen/AArch64/ |
| neon-add-pairwise.ll | 1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
13 declare <16 x i8> @llvm.arm.neon.vpadd.v16i8(<16 x i8>, <16 x i8>)
17 %tmp1 = call <16 x i8> @llvm.arm.neon.vpadd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
22 declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>)
26 %tmp1 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
31 declare <8 x i16> @llvm.arm.neon.vpadd.v8i16(<8 x i16>, <8 x i16>)
35 %tmp1 = call <8 x i16> @llvm.arm.neon.vpadd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
40 declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>
[all...] |
| neon-frsqrt-frecp.ll | 1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
5 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>)
6 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>)
7 declare <2 x double> @llvm.arm.neon.vrsqrts.v2f64(<2 x double>, <2 x double>)
12 %val = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %lhs, <2 x float> %rhs)
19 %val = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %lhs, <4 x float> %rhs)
26 %val = call <2 x double> @llvm.arm.neon.vrsqrts.v2f64(<2 x double> %lhs, <2 x double> %rhs)
30 declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>)
31 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>)
32 declare <2 x double> @llvm.arm.neon.vrecps.v2f64(<2 x double>, <2 x double>
[all...] |
| /external/clang/test/CodeGen/ |
| arm-neon-misc.c | 12 // Radar 11998303: Avoid using i64 types for vld1q_lane and vst1q_lane Neon
17 // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64
21 // CHECK: call void @llvm.arm.neon.vst1.v1i64
27 // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64
30 // CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64
|
| /external/llvm/test/Transforms/InstCombine/ |
| neon-intrinsics.ll | 3 ; The alignment arguments for NEON load/store intrinsics can be increased
15 %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* bitcast ([8 x i32]* @x to i8*), i32 1)
20 call void @llvm.arm.neon.vst4.v2i32(i8* bitcast ([8 x i32]* @y to i8*), <2 x i32> %tmp2, <2 x i32> %tmp3, <2 x i32> %tmp4, <2 x i32> %tmp5, i32 1)
24 declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*, i32) nounwind readonly
25 declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
|
