/external/llvm/lib/Target/Hexagon/ |
HexagonCFGOptimizer.cpp | 75 int NewOpcode = 0; 78 NewOpcode = Hexagon::JMP_f; 82 NewOpcode = Hexagon::JMP_t; 86 NewOpcode = Hexagon::JMP_fnew_t; 90 NewOpcode = Hexagon::JMP_tnew_t; 97 MI->setDesc(QII->get(NewOpcode));
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HexagonVLIWPacketizer.cpp | 438 int NewOpcode; 440 NewOpcode = QII->GetDotNewPredOp(MI, MBPI); 442 NewOpcode = QII->GetDotNewOp(MI); 443 MI->setDesc(QII->get(NewOpcode)); 450 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); 451 MI->setDesc(QII->get(NewOpcode)); 771 int NewOpcode = QII->GetDotNewOp(MI); 772 const MCInstrDesc &desc = QII->get(NewOpcode); [all...] |
HexagonInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 219 int NewOpcode; 221 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 226 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 227 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 232 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 233 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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/dalvik/dx/src/com/android/dx/ssa/ |
LiteralOpUpgrader.java | 182 * @param newOpcode A RegOp from {@link RegOps} 186 RegisterSpecList newSources, int newOpcode, Constant cst) { 189 Rop newRop = Rops.ropFor(newOpcode, insn.getResult(), newSources, cst);
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EscapeAnalysis.java | 780 * @param newOpcode opcode of new instruction 784 RegisterSpecList newSources, RegisterSpec newResult, int newOpcode, [all...] |
/external/dexmaker/src/dx/java/com/android/dx/ssa/ |
LiteralOpUpgrader.java | 183 * @param newOpcode A RegOp from {@link RegOps} 187 RegisterSpecList newSources, int newOpcode, Constant cst) { 190 Rop newRop = Rops.ropFor(newOpcode, insn.getResult(), newSources, cst);
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EscapeAnalysis.java | 781 * @param newOpcode opcode of new instruction 785 RegisterSpecList newSources, RegisterSpec newResult, int newOpcode, [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZInstrInfo.cpp | 37 // each having the opcode given by NewOpcode. 39 unsigned NewOpcode) const { 61 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 62 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); 80 assert(NewOpcode && "No support for huge argument lists yet"); 81 MI->setDesc(get(NewOpcode)); 503 unsigned NewOpcode; 505 NewOpcode = SystemZ::RISBG; 507 NewOpcode = SystemZ::RISBLG32 [all...] |
SystemZFrameLowering.cpp | 436 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); 440 if (!NewOpcode) { 445 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); 446 assert(NewOpcode && "No restore instruction available"); 449 MBBI->setDesc(ZII->get(NewOpcode));
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SystemZInstrInfo.h | 109 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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/external/proguard/src/proguard/optimize/evaluation/ |
EvaluationShrinker.java | [all...] |
/external/llvm/lib/Target/R600/ |
AMDILCFGStructurizer.cpp | 224 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, 226 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, 228 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode); 229 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode, 232 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, 234 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum); 465 int NewOpcode, DebugLoc DL) { 467 ->CreateMachineInstr(TII->get(NewOpcode), DL); 474 int NewOpcode, DebugLoc DL) { 476 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL) [all...] |
SIISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCCodeEmitter.cpp | 214 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); 215 if (NewOpcode != -1) { 216 Opcode = NewOpcode; 217 TmpInst.setOpcode (NewOpcode);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
AMDILCFGStructurizer.cpp | [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
AMDILCFGStructurizer.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86MCInstLower.cpp | 260 unsigned NewOpcode = 0; 267 NewOpcode = X86::CBW; 271 NewOpcode = X86::CWDE; 275 NewOpcode = X86::CDQE; 279 if (NewOpcode != 0) { 281 Inst.setOpcode(NewOpcode);
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X86InstrInfo.cpp | [all...] |
/dalvik/dx/src/com/android/dx/dex/code/ |
OutputFinisher.java | 460 Dop newOpcode = findOpcodeForInsn(insn, originalOpcode); 462 if (newOpcode == null) { 473 } else if (originalOpcode == newOpcode) { 477 opcodes[i] = newOpcode;
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/external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
OutputFinisher.java | 460 Dop newOpcode = findOpcodeForInsn(insn, originalOpcode); 462 if (newOpcode == null) { 473 } else if (originalOpcode == newOpcode) { 477 opcodes[i] = newOpcode;
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
PPCAsmParser.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCAsmPrinter.cpp | 672 unsigned NewOpcode = 676 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) 686 unsigned NewOpcode = 692 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) [all...] |
PPCRegisterInfo.cpp | 671 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 672 MI.setDesc(TII.get(NewOpcode));
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/external/llvm/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | [all...] |