| /external/llvm/test/FileCheck/ |
| check-dag.txt | 16 ; CHECK-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; CHECK: mul r5, [[REG1]], [[REG2]]
20 ; CHECK-DAG: mul [[REG2:r[0-9]+]], r3, r4
21 ; CHECK: add r5, [[REG1]], [[REG2]]
24 ; CHECK-DAG: add [[REG2:r[0-9]+]], r3, r4
26 ; CHECK-DAG: mul r5, [[REG1]], [[REG2]]
|
| regex-brackets.txt | 6 ; CHECK: op [[REG2:r[0-9]]], [x [[REG]]]
|
| check-dag-xfails.txt | 16 ; X1-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; X1: mul r5, [[REG1]], [[REG2]]
28 ; X2-DAG: mul [[REG2:r[0-9]+]], r3, r4
29 ; X2: add r5, [[REG1]], [[REG2]]
40 ; X3-DAG: add [[REG2:r[0-9]+]], r3, r4
41 ; X3-DAG: mul r5, [[REG1]], [[REG2]]
53 ; X4-DAG: add [[REG2:r[0-9]+]], r3, r4
55 ; X4-DAG: mul r5, [[REG1]], [[REG2]]
67 ; X5-DAG: add [[REG2:r[0-9]+]], r3, r4
69 ; X5-DAG: mul r5, [[REG1]], [[REG2]]
[all...] |
| var-ref-same-line.txt | 10 ; CHECK: op3 [[REG1:r[0-9]+]], [[REG2:r[0-9]+]], [[REG1]], [[REG2]]
|
| /external/llvm/test/CodeGen/Thumb/ |
| 2012-04-26-M0ISelBug.ll | 7 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
8 ; CHECK: eors [[REG1]], [[REG2]]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| tls.ll | 13 ;OPT0-NEXT: li [[REG2:[0-9]+]], 42
15 ;OPT0: stw [[REG2]], 0([[REG1]])
17 ;OPT1-NEXT: li [[REG2:[0-9]+]], 42
18 ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
|
| anon_aggr.ll | 33 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
36 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
43 ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
46 ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
66 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
67 ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
68 ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
75 ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
78 ; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
80 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]
[all...] |
| mcm-2.ll | 22 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
23 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
24 ; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
31 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
32 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
33 ; LARGE: stw {{[0-9]+}}, 0([[REG2]])
|
| mcm-3.ll | 22 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
23 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
24 ; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
33 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
34 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
35 ; LARGE: stw {{[0-9]+}}, 0([[REG2]])
|
| ppc32-vacopy.ll | 20 ; CHECK: lwz [[REG2:[0-9]+]], {{.*}}
23 ; CHECK: stw [[REG2]], {{.*}}
|
| tls-2.ll | 11 ;CHECK-NEXT: li [[REG2:[0-9]+]], 42
12 ;CHECK-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
|
| mcm-4.ll | 19 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
20 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
26 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
27 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
|
| i32-to-float.ll | 15 ; CHECK: lfd [[REG2:[0-9]+]],
16 ; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
23 ; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
24 ; CHECK-PWR6: frsp 1, [[REG2]]
42 ; CHECK: lfd [[REG2:[0-9]+]],
43 ; CHECK: fcfid 1, [[REG2]]
|
| mcm-1.ll | 22 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
23 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
24 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
|
| mcm-6.ll | 22 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
23 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
24 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
|
| mcm-9.ll | 23 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
24 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
25 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
|
| mcm-default.ll | 21 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
22 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
23 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
|
| vaddsplat.ll | 86 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
88 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
98 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
100 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
110 ; CHECK: vspltish [[REG2:[0-9]+]], -16
112 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
122 ; CHECK: vspltish [[REG2:[0-9]+]], -16
124 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
134 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
136 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
[all...] |
| tls-ie.ll | 20 ; CHECK: ld [[REG2:[0-9]+]], a@got@tprel@l([[REG1]])
21 ; CHECK: add {{[0-9]+}}, [[REG2]], a@tls
|
| tls-ld-2.ll | 23 ; CHECK: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
24 ; CHECK-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
|
| tls-ld.ll | 23 ; CHECK: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
24 ; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
|
| /external/llvm/test/CodeGen/ARM/ |
| atomic-64bit.ll | 7 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
9 ; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
17 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
19 ; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
32 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
34 ; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
42 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
44 ; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
57 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
59 ; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
[all...] |
| fast-isel-pic.ll | 23 ; ARMv7: movw [[reg2:r[0-9]+]],
24 ; ARMv7: movt [[reg2]],
25 ; ARMv7: add [[reg2]], pc, [[reg2]]
27 ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
29 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
|
| fcopysign.ll | 25 ; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
26 ; HARD: vshl.i64 [[REG2]], [[REG2]], #32
27 ; HARD: vbsl [[REG2]], d1, d0
|
| /external/llvm/test/CodeGen/Hexagon/ |
| newvaluejump2.ll | 9 %Reg2 = alloca i8, align 1
10 %0 = load i8* %Reg2, align 1
|
